[LSF/MM TOPIC] Impact on core mm from new hardware features

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I'd like to have a session about new hardware features that may will
have an impact on core memory management.  This session would have two
goals: one to ensure that the OS-agnostic MM crowd understands what the
architectures are going to be throwing their way.  Second, that the
different arch-specific folks can look for commonalities which could
enable shared infrastructure.

There should be enough x86 folks around, but I'd love to hear from the
ARM and powerpc people as well.

Here are a few mostly Intel-specific things I'd like to discuss.
However, all of these either have analogs on other architectures or are
implemented by other x86 vendors.

 * Shadow Stacks - requires new Copy-on-Read memory type.  Creates
   application mappings which are effectively PROT_NONE, but which are
   implicitly accessible by the hardware.
 * Linear Address Masking (LAM) - Similar to ARM's Top Byte Ignore
   (TBI).  Repurpose some virtual address bits to store metadata.  Intel
   implementation can sacrifice user address space.  Offloads some of
   the work the compiler does in ASAN implementations.
 * Supervisor Protection Keys - Extends Memory Protection Keys (pkeys)
   to kernel mappings.
 * TDX - VMs that don't trust the hypervisor.  Requires unmapping guest
   memory from userspace and possibly the host kernel.

I would also expect there to be a few more things that will become
available to discuss between now and the conference.





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