Hi Christoph, On 14.06.2021 17:36, Christoph Hellwig wrote: > On Mon, Jun 14, 2021 at 04:34:05PM +0100, Robin Murphy wrote: >>> Looking at the rmem_dma_device_init() -> dma_init_coherent_memory(), it >>> ends up calling memremap(MEMREMAP_WC) which would warn if it intersects >>> with system RAM regardless of the architecture. If the memory region is >>> nomap, it doesn't end up as IORESOURCE_SYSTEM_RAM, so memremap() won't >>> warn. But why is this specific only to arm (or arm64)? >> Didn't some ARMv7 implementations permit unexpected cache hits for the >> non-cacheable address if the same PA has been speculatively fetched via the >> cacheable alias? > If we care about that we need to change these platforms to change the > cache attributes of the kernel direct mapping instead of using vmap. > We already have code to do that for openrisc, someone just needs to > write the glue code for other platforms. ARAIR there is a problem with changing cache attributes of the direct mappings on ARM 32bit. The whole lowmem is mapped with 2M 'section' mappings. Changing cache attributes causes 2 issues. First - one would need to split 2M entry into 4K entries. Second - 2M section mappings for the whole lowmem area are located in the per-process page tables. Changing the cache attributes would require locking all processes and iterating over their page table entries, which is a huge task. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland
