On 6/13/21 4:20 PM, Matthew Wilcox wrote:
On Sun, Jun 13, 2021 at 02:36:13PM +0530, Aneesh Kumar K.V wrote:
IIUC the reason why we do have pmd_pgtable() is that pgtable_t type
is arch dependent. On some architecture it is pte_t * and on the other
struct page *. The reason being highmem and level 4 page table can
be located in highmem.
That is ahistorical. See 2f569afd9ced9ebec9a6eb3dbf6f83429be0a7b4 --
we have pgtable_t for the benefit of s390's crazy sub-page page table
sizes.
That is also true with ppc64. We do sub-page page table size. I was
trying to explain why it can't be pte_t * everywhere and why we have
it as struct page *.
Also, please stop numbering page tables upside down. PTEs are first
level, not fourth.
POWER ISA do name it the other way. I also see some pages explaining
levels the other way
https://www.bottomupcs.com/virtual_memory_linux.xhtml
whereas
https://en.wikipedia.org/wiki/Intel_5-level_paging#/media/File:Page_Tables_(5_levels).svg
I am pretty sure I had commits that explained page table level as I did
in this thread. I will switch to your suggestion in further discussions.
May be the best solution is to attribute it with more details like level
1 (pte_t *)?
-aneesh
