tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 5d765451c2409e63563fa6a3e8005bd03ab9e82f commit: cd6d421e3d1ad5926b74091254e345db730e7706 [3447/5003] drm/amd/display: Initial DC support for Beige Goby config: i386-randconfig-r036-20210525 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=cd6d421e3d1ad5926b74091254e345db730e7706 git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout cd6d421e3d1ad5926b74091254e345db730e7706 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:306:19: note: in expansion of macro 'BASE_INNER' 306 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:321:19: note: in expansion of macro 'BASE' 321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:528:2: note: in expansion of macro 'SRII' 528 | SRII(PIXEL_RATE_CNTL, blk, 1) | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:506:2: note: in expansion of macro 'HWSEQ_PIXEL_RATE_REG_LIST_303' 506 | HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:573:3: note: in expansion of macro 'HWSEQ_DCN303_REG_LIST' 573 | HWSEQ_DCN303_REG_LIST() | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:371:52: warning: initialized field overwritten [-Woverride-init] 371 | #define DCN_BASE__INST0_SEG1 0x000000C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG1' 304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:306:19: note: in expansion of macro 'BASE_INNER' 306 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:321:19: note: in expansion of macro 'BASE' 321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:531:2: note: in expansion of macro 'SRII' 531 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:507:2: note: in expansion of macro 'HWSEQ_PHYPLL_REG_LIST_303' 507 | HWSEQ_PHYPLL_REG_LIST_303(OTG), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:573:3: note: in expansion of macro 'HWSEQ_DCN303_REG_LIST' 573 | HWSEQ_DCN303_REG_LIST() | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:371:52: note: (near initialization for 'hwseq_reg.PHYPLL_PIXEL_RATE_CNTL[0]') 371 | #define DCN_BASE__INST0_SEG1 0x000000C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG1' 304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:306:19: note: in expansion of macro 'BASE_INNER' 306 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:321:19: note: in expansion of macro 'BASE' 321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:531:2: note: in expansion of macro 'SRII' 531 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:507:2: note: in expansion of macro 'HWSEQ_PHYPLL_REG_LIST_303' 507 | HWSEQ_PHYPLL_REG_LIST_303(OTG), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:573:3: note: in expansion of macro 'HWSEQ_DCN303_REG_LIST' 573 | HWSEQ_DCN303_REG_LIST() | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:371:52: warning: initialized field overwritten [-Woverride-init] 371 | #define DCN_BASE__INST0_SEG1 0x000000C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG1' 304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:306:19: note: in expansion of macro 'BASE_INNER' 306 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:321:19: note: in expansion of macro 'BASE' 321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:532:2: note: in expansion of macro 'SRII' 532 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:507:2: note: in expansion of macro 'HWSEQ_PHYPLL_REG_LIST_303' 507 | HWSEQ_PHYPLL_REG_LIST_303(OTG), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:573:3: note: in expansion of macro 'HWSEQ_DCN303_REG_LIST' 573 | HWSEQ_DCN303_REG_LIST() | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:371:52: note: (near initialization for 'hwseq_reg.PHYPLL_PIXEL_RATE_CNTL[1]') 371 | #define DCN_BASE__INST0_SEG1 0x000000C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG1' 304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:306:19: note: in expansion of macro 'BASE_INNER' 306 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:321:19: note: in expansion of macro 'BASE' 321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:532:2: note: in expansion of macro 'SRII' 532 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:507:2: note: in expansion of macro 'HWSEQ_PHYPLL_REG_LIST_303' 507 | HWSEQ_PHYPLL_REG_LIST_303(OTG), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:573:3: note: in expansion of macro 'HWSEQ_DCN303_REG_LIST' 573 | HWSEQ_DCN303_REG_LIST() | ^~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:68: >> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7607:111: warning: initialized field overwritten [-Woverride-init] 7607 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:408:2: note: in expansion of macro 'HUBP_SF' 408 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7607:111: note: (near initialization for 'hubp_shift.REFCYC_PER_REQ_DELIVERY') 7607 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:408:2: note: in expansion of macro 'HUBP_SF' 408 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7608:111: warning: initialized field overwritten [-Woverride-init] 7608 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:409:2: note: in expansion of macro 'HUBP_SF' 409 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7608:111: note: (near initialization for 'hubp_shift.QoS_LEVEL_FIXED') 7608 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:409:2: note: in expansion of macro 'HUBP_SF' 409 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7609:111: warning: initialized field overwritten [-Woverride-init] 7609 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:410:2: note: in expansion of macro 'HUBP_SF' 410 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7609:111: note: (near initialization for 'hubp_shift.QoS_RAMP_DISABLE') 7609 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:410:2: note: in expansion of macro 'HUBP_SF' 410 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:606:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30' 606 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h:7614:111: warning: initialized field overwritten [-Woverride-init] 7614 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:253:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT' 253 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:411:2: note: in expansion of macro 'HUBP_SF' 411 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:193:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM' 193 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ -- >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_init.c:30:6: warning: no previous prototype for 'dcn303_hw_sequencer_construct' [-Wmissing-prototypes] 30 | void dcn303_hw_sequencer_construct(struct dc *dc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +7607 drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h 8198ace7a074de Aurabindo Pillai 2021-03-15 7387 8198ace7a074de Aurabindo Pillai 2021-03-15 7388 8198ace7a074de Aurabindo Pillai 2021-03-15 7389 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 8198ace7a074de Aurabindo Pillai 2021-03-15 7390 //HUBPREQ0_DCSURF_SURFACE_PITCH 8198ace7a074de Aurabindo Pillai 2021-03-15 7391 #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7392 #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7393 #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7394 #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7395 //HUBPREQ0_DCSURF_SURFACE_PITCH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7396 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7397 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7398 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7399 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7400 //HUBPREQ0_VMID_SETTINGS_0 8198ace7a074de Aurabindo Pillai 2021-03-15 7401 #define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7402 #define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL 8198ace7a074de Aurabindo Pillai 2021-03-15 7403 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 8198ace7a074de Aurabindo Pillai 2021-03-15 7404 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7405 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7406 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7407 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7408 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7409 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7410 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7411 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7412 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7413 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7414 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7415 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 8198ace7a074de Aurabindo Pillai 2021-03-15 7416 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7417 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7418 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7419 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7420 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7421 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7422 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7423 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7424 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7425 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7426 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7427 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 8198ace7a074de Aurabindo Pillai 2021-03-15 7428 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7429 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7430 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7431 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7432 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7433 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7434 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7435 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7436 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7437 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7438 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7439 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 8198ace7a074de Aurabindo Pillai 2021-03-15 7440 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7441 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7442 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7443 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7444 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7445 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7446 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7447 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7448 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7449 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7450 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7451 //HUBPREQ0_DCSURF_SURFACE_CONTROL 8198ace7a074de Aurabindo Pillai 2021-03-15 7452 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7453 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 8198ace7a074de Aurabindo Pillai 2021-03-15 7454 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 8198ace7a074de Aurabindo Pillai 2021-03-15 7455 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 8198ace7a074de Aurabindo Pillai 2021-03-15 7456 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 8198ace7a074de Aurabindo Pillai 2021-03-15 7457 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7458 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 8198ace7a074de Aurabindo Pillai 2021-03-15 7459 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa 8198ace7a074de Aurabindo Pillai 2021-03-15 7460 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc 8198ace7a074de Aurabindo Pillai 2021-03-15 7461 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd 8198ace7a074de Aurabindo Pillai 2021-03-15 7462 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7463 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 8198ace7a074de Aurabindo Pillai 2021-03-15 7464 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 8198ace7a074de Aurabindo Pillai 2021-03-15 7465 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 8198ace7a074de Aurabindo Pillai 2021-03-15 7466 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L 8198ace7a074de Aurabindo Pillai 2021-03-15 7467 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L 8198ace7a074de Aurabindo Pillai 2021-03-15 7468 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL 8198ace7a074de Aurabindo Pillai 2021-03-15 7469 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L 8198ace7a074de Aurabindo Pillai 2021-03-15 7470 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L 8198ace7a074de Aurabindo Pillai 2021-03-15 7471 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L 8198ace7a074de Aurabindo Pillai 2021-03-15 7472 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L 8198ace7a074de Aurabindo Pillai 2021-03-15 7473 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L 8198ace7a074de Aurabindo Pillai 2021-03-15 7474 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7475 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7476 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7477 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7478 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7479 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7480 //HUBPREQ0_DCSURF_FLIP_CONTROL 8198ace7a074de Aurabindo Pillai 2021-03-15 7481 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7482 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 8198ace7a074de Aurabindo Pillai 2021-03-15 7483 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 8198ace7a074de Aurabindo Pillai 2021-03-15 7484 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7485 #define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 8198ace7a074de Aurabindo Pillai 2021-03-15 7486 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc 8198ace7a074de Aurabindo Pillai 2021-03-15 7487 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7488 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 8198ace7a074de Aurabindo Pillai 2021-03-15 7489 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 8198ace7a074de Aurabindo Pillai 2021-03-15 7490 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 8198ace7a074de Aurabindo Pillai 2021-03-15 7491 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L 8198ace7a074de Aurabindo Pillai 2021-03-15 7492 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L 8198ace7a074de Aurabindo Pillai 2021-03-15 7493 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L 8198ace7a074de Aurabindo Pillai 2021-03-15 7494 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L 8198ace7a074de Aurabindo Pillai 2021-03-15 7495 #define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L 8198ace7a074de Aurabindo Pillai 2021-03-15 7496 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7497 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7498 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7499 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7500 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7501 //HUBPREQ0_DCSURF_FLIP_CONTROL2 8198ace7a074de Aurabindo Pillai 2021-03-15 7502 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7503 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7504 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 8198ace7a074de Aurabindo Pillai 2021-03-15 7505 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa 8198ace7a074de Aurabindo Pillai 2021-03-15 7506 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc 8198ace7a074de Aurabindo Pillai 2021-03-15 7507 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7508 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L 8198ace7a074de Aurabindo Pillai 2021-03-15 7509 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L 8198ace7a074de Aurabindo Pillai 2021-03-15 7510 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L 8198ace7a074de Aurabindo Pillai 2021-03-15 7511 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7512 //HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 8198ace7a074de Aurabindo Pillai 2021-03-15 7513 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7514 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 8198ace7a074de Aurabindo Pillai 2021-03-15 7515 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 8198ace7a074de Aurabindo Pillai 2021-03-15 7516 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 8198ace7a074de Aurabindo Pillai 2021-03-15 7517 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7518 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 8198ace7a074de Aurabindo Pillai 2021-03-15 7519 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7520 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 8198ace7a074de Aurabindo Pillai 2021-03-15 7521 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 8198ace7a074de Aurabindo Pillai 2021-03-15 7522 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 8198ace7a074de Aurabindo Pillai 2021-03-15 7523 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L 8198ace7a074de Aurabindo Pillai 2021-03-15 7524 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L 8198ace7a074de Aurabindo Pillai 2021-03-15 7525 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L 8198ace7a074de Aurabindo Pillai 2021-03-15 7526 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L 8198ace7a074de Aurabindo Pillai 2021-03-15 7527 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L 8198ace7a074de Aurabindo Pillai 2021-03-15 7528 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L 8198ace7a074de Aurabindo Pillai 2021-03-15 7529 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7530 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7531 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7532 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7533 //HUBPREQ0_DCSURF_SURFACE_INUSE 8198ace7a074de Aurabindo Pillai 2021-03-15 7534 #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7535 #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7536 //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7537 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7538 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7539 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7540 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7541 //HUBPREQ0_DCSURF_SURFACE_INUSE_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7542 #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7543 #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7544 //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7545 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7546 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7547 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7548 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7549 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 8198ace7a074de Aurabindo Pillai 2021-03-15 7550 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7551 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7552 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 8198ace7a074de Aurabindo Pillai 2021-03-15 7553 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7554 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7555 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7556 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7557 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7558 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7559 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7560 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7561 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7562 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7563 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7564 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7565 //HUBPREQ0_DCN_EXPANSION_MODE 8198ace7a074de Aurabindo Pillai 2021-03-15 7566 #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7567 #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 8198ace7a074de Aurabindo Pillai 2021-03-15 7568 #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 8198ace7a074de Aurabindo Pillai 2021-03-15 7569 #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 8198ace7a074de Aurabindo Pillai 2021-03-15 7570 #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L 8198ace7a074de Aurabindo Pillai 2021-03-15 7571 #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL 8198ace7a074de Aurabindo Pillai 2021-03-15 7572 #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L 8198ace7a074de Aurabindo Pillai 2021-03-15 7573 #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L 8198ace7a074de Aurabindo Pillai 2021-03-15 7574 //HUBPREQ0_DCN_TTU_QOS_WM 8198ace7a074de Aurabindo Pillai 2021-03-15 7575 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7576 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7577 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7578 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7579 //HUBPREQ0_DCN_GLOBAL_TTU_CNTL 8198ace7a074de Aurabindo Pillai 2021-03-15 7580 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7581 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b 8198ace7a074de Aurabindo Pillai 2021-03-15 7582 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7583 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7584 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7585 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7586 //HUBPREQ0_DCN_SURF0_TTU_CNTL0 8198ace7a074de Aurabindo Pillai 2021-03-15 7587 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7588 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7589 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7590 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7591 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7592 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7593 //HUBPREQ0_DCN_SURF0_TTU_CNTL1 8198ace7a074de Aurabindo Pillai 2021-03-15 7594 #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7595 #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7596 //HUBPREQ0_DCN_SURF1_TTU_CNTL0 8198ace7a074de Aurabindo Pillai 2021-03-15 7597 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7598 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7599 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7600 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7601 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7602 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7603 //HUBPREQ0_DCN_SURF1_TTU_CNTL1 8198ace7a074de Aurabindo Pillai 2021-03-15 7604 #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7605 #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7606 //HUBPREQ0_DCN_CUR0_TTU_CNTL0 8198ace7a074de Aurabindo Pillai 2021-03-15 @7607 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7608 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7609 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7610 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7611 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7612 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7613 //HUBPREQ0_DCN_CUR0_TTU_CNTL1 8198ace7a074de Aurabindo Pillai 2021-03-15 7614 #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7615 #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7616 //HUBPREQ0_DCN_CUR1_TTU_CNTL0 8198ace7a074de Aurabindo Pillai 2021-03-15 7617 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7618 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7619 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c 8198ace7a074de Aurabindo Pillai 2021-03-15 7620 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7621 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7622 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7623 //HUBPREQ0_DCN_CUR1_TTU_CNTL1 8198ace7a074de Aurabindo Pillai 2021-03-15 7624 #define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7625 #define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7626 //HUBPREQ0_DCN_DMDATA_VM_CNTL 8198ace7a074de Aurabindo Pillai 2021-03-15 7627 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7628 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7629 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 8198ace7a074de Aurabindo Pillai 2021-03-15 7630 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7631 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 8198ace7a074de Aurabindo Pillai 2021-03-15 7632 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a 8198ace7a074de Aurabindo Pillai 2021-03-15 7633 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f 8198ace7a074de Aurabindo Pillai 2021-03-15 7634 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7635 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7636 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7637 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7638 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7639 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7640 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7641 //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 8198ace7a074de Aurabindo Pillai 2021-03-15 7642 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7643 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7644 //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 8198ace7a074de Aurabindo Pillai 2021-03-15 7645 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7646 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7647 //HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 8198ace7a074de Aurabindo Pillai 2021-03-15 7648 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7649 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 8198ace7a074de Aurabindo Pillai 2021-03-15 7650 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 8198ace7a074de Aurabindo Pillai 2021-03-15 7651 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 8198ace7a074de Aurabindo Pillai 2021-03-15 7652 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 8198ace7a074de Aurabindo Pillai 2021-03-15 7653 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 8198ace7a074de Aurabindo Pillai 2021-03-15 7654 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 8198ace7a074de Aurabindo Pillai 2021-03-15 7655 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 8198ace7a074de Aurabindo Pillai 2021-03-15 7656 //HUBPREQ0_BLANK_OFFSET_0 8198ace7a074de Aurabindo Pillai 2021-03-15 7657 #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7658 #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7659 #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7660 #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7661 //HUBPREQ0_BLANK_OFFSET_1 8198ace7a074de Aurabindo Pillai 2021-03-15 7662 #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7663 #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7664 //HUBPREQ0_DST_DIMENSIONS 8198ace7a074de Aurabindo Pillai 2021-03-15 7665 #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7666 #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7667 //HUBPREQ0_DST_AFTER_SCALER 8198ace7a074de Aurabindo Pillai 2021-03-15 7668 #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7669 #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7670 #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7671 #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7672 //HUBPREQ0_PREFETCH_SETTINGS 8198ace7a074de Aurabindo Pillai 2021-03-15 7673 #define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7674 #define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7675 #define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7676 #define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7677 //HUBPREQ0_PREFETCH_SETTINGS_C 8198ace7a074de Aurabindo Pillai 2021-03-15 7678 #define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7679 #define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7680 //HUBPREQ0_VBLANK_PARAMETERS_0 8198ace7a074de Aurabindo Pillai 2021-03-15 7681 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7682 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7683 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL 8198ace7a074de Aurabindo Pillai 2021-03-15 7684 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L 8198ace7a074de Aurabindo Pillai 2021-03-15 7685 //HUBPREQ0_VBLANK_PARAMETERS_1 8198ace7a074de Aurabindo Pillai 2021-03-15 7686 #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7687 #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7688 //HUBPREQ0_VBLANK_PARAMETERS_2 8198ace7a074de Aurabindo Pillai 2021-03-15 7689 #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7690 #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7691 //HUBPREQ0_VBLANK_PARAMETERS_3 8198ace7a074de Aurabindo Pillai 2021-03-15 7692 #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7693 #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7694 //HUBPREQ0_VBLANK_PARAMETERS_4 8198ace7a074de Aurabindo Pillai 2021-03-15 7695 #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7696 #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7697 //HUBPREQ0_FLIP_PARAMETERS_0 8198ace7a074de Aurabindo Pillai 2021-03-15 7698 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7699 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7700 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL 8198ace7a074de Aurabindo Pillai 2021-03-15 7701 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L 8198ace7a074de Aurabindo Pillai 2021-03-15 7702 //HUBPREQ0_FLIP_PARAMETERS_1 8198ace7a074de Aurabindo Pillai 2021-03-15 7703 #define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7704 #define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7705 //HUBPREQ0_FLIP_PARAMETERS_2 8198ace7a074de Aurabindo Pillai 2021-03-15 7706 #define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7707 #define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7708 //HUBPREQ0_NOM_PARAMETERS_0 8198ace7a074de Aurabindo Pillai 2021-03-15 7709 #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7710 #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7711 //HUBPREQ0_NOM_PARAMETERS_1 8198ace7a074de Aurabindo Pillai 2021-03-15 7712 #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7713 #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7714 //HUBPREQ0_NOM_PARAMETERS_2 8198ace7a074de Aurabindo Pillai 2021-03-15 7715 #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7716 #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7717 //HUBPREQ0_NOM_PARAMETERS_3 8198ace7a074de Aurabindo Pillai 2021-03-15 7718 #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7719 #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7720 //HUBPREQ0_NOM_PARAMETERS_4 8198ace7a074de Aurabindo Pillai 2021-03-15 7721 #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7722 #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7723 //HUBPREQ0_NOM_PARAMETERS_5 8198ace7a074de Aurabindo Pillai 2021-03-15 7724 #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7725 #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7726 //HUBPREQ0_NOM_PARAMETERS_6 8198ace7a074de Aurabindo Pillai 2021-03-15 7727 #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7728 #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7729 //HUBPREQ0_NOM_PARAMETERS_7 8198ace7a074de Aurabindo Pillai 2021-03-15 7730 #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7731 #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7732 //HUBPREQ0_PER_LINE_DELIVERY_PRE 8198ace7a074de Aurabindo Pillai 2021-03-15 7733 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7734 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7735 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7736 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7737 //HUBPREQ0_PER_LINE_DELIVERY 8198ace7a074de Aurabindo Pillai 2021-03-15 7738 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7739 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7740 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7741 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7742 //HUBPREQ0_CURSOR_SETTINGS 8198ace7a074de Aurabindo Pillai 2021-03-15 7743 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7744 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7745 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 8198ace7a074de Aurabindo Pillai 2021-03-15 7746 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 8198ace7a074de Aurabindo Pillai 2021-03-15 7747 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7748 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L 8198ace7a074de Aurabindo Pillai 2021-03-15 7749 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7750 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7751 //HUBPREQ0_REF_FREQ_TO_PIX_FREQ 8198ace7a074de Aurabindo Pillai 2021-03-15 7752 #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7753 #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7754 //HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 8198ace7a074de Aurabindo Pillai 2021-03-15 7755 #define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7756 #define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7757 //HUBPREQ0_HUBPREQ_MEM_PWR_CTRL 8198ace7a074de Aurabindo Pillai 2021-03-15 7758 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7759 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 8198ace7a074de Aurabindo Pillai 2021-03-15 7760 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 8198ace7a074de Aurabindo Pillai 2021-03-15 7761 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 8198ace7a074de Aurabindo Pillai 2021-03-15 7762 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 8198ace7a074de Aurabindo Pillai 2021-03-15 7763 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa 8198ace7a074de Aurabindo Pillai 2021-03-15 7764 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc 8198ace7a074de Aurabindo Pillai 2021-03-15 7765 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe 8198ace7a074de Aurabindo Pillai 2021-03-15 7766 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L 8198ace7a074de Aurabindo Pillai 2021-03-15 7767 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L 8198ace7a074de Aurabindo Pillai 2021-03-15 7768 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L 8198ace7a074de Aurabindo Pillai 2021-03-15 7769 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L 8198ace7a074de Aurabindo Pillai 2021-03-15 7770 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L 8198ace7a074de Aurabindo Pillai 2021-03-15 7771 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L 8198ace7a074de Aurabindo Pillai 2021-03-15 7772 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7773 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L 8198ace7a074de Aurabindo Pillai 2021-03-15 7774 //HUBPREQ0_HUBPREQ_MEM_PWR_STATUS 8198ace7a074de Aurabindo Pillai 2021-03-15 7775 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7776 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 8198ace7a074de Aurabindo Pillai 2021-03-15 7777 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 8198ace7a074de Aurabindo Pillai 2021-03-15 7778 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 8198ace7a074de Aurabindo Pillai 2021-03-15 7779 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L 8198ace7a074de Aurabindo Pillai 2021-03-15 7780 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL 8198ace7a074de Aurabindo Pillai 2021-03-15 7781 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L 8198ace7a074de Aurabindo Pillai 2021-03-15 7782 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L 8198ace7a074de Aurabindo Pillai 2021-03-15 7783 //HUBPREQ0_VBLANK_PARAMETERS_5 8198ace7a074de Aurabindo Pillai 2021-03-15 7784 #define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7785 #define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7786 //HUBPREQ0_VBLANK_PARAMETERS_6 8198ace7a074de Aurabindo Pillai 2021-03-15 7787 #define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7788 #define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7789 //HUBPREQ0_FLIP_PARAMETERS_3 8198ace7a074de Aurabindo Pillai 2021-03-15 7790 #define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7791 #define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7792 //HUBPREQ0_FLIP_PARAMETERS_4 8198ace7a074de Aurabindo Pillai 2021-03-15 7793 #define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7794 #define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7795 //HUBPREQ0_FLIP_PARAMETERS_5 8198ace7a074de Aurabindo Pillai 2021-03-15 7796 #define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7797 #define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7798 //HUBPREQ0_FLIP_PARAMETERS_6 8198ace7a074de Aurabindo Pillai 2021-03-15 7799 #define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 8198ace7a074de Aurabindo Pillai 2021-03-15 7800 #define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL 8198ace7a074de Aurabindo Pillai 2021-03-15 7801 8198ace7a074de Aurabindo Pillai 2021-03-15 7802 :::::: The code at line 7607 was first introduced by commit :::::: 8198ace7a074de4dfdc10885ccf081476b50d41b drm/amd/display: Add register definitions for Beige Goby :::::: TO: Aurabindo Pillai <aurabindo.pillai@xxxxxxx> :::::: CC: Alex Deucher <alexander.deucher@xxxxxxx> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
Attachment:
.config.gz
Description: application/gzip
