From: Matthew Wilcox
> Sent: 14 April 2021 22:36
>
> On Wed, Apr 14, 2021 at 09:13:22PM +0200, Jesper Dangaard Brouer wrote:
> > (If others want to reproduce). First I could not reproduce on ARM32.
> > Then I found out that enabling CONFIG_XEN on ARCH=arm was needed to
> > cause the issue by enabling CONFIG_ARCH_DMA_ADDR_T_64BIT.
>
> hmmm ... you should be able to provoke it by enabling ARM_LPAE,
> which selects PHYS_ADDR_T_64BIT, and
>
> config ARCH_DMA_ADDR_T_64BIT
> def_bool 64BIT || PHYS_ADDR_T_64BIT
>
> > struct page {
> > long unsigned int flags; /* 0 4 */
> >
> > /* XXX 4 bytes hole, try to pack */
> >
> > union {
> > struct {
> > struct list_head lru; /* 8 8 */
> > struct address_space * mapping; /* 16 4 */
> > long unsigned int index; /* 20 4 */
> > long unsigned int private; /* 24 4 */
> > }; /* 8 20 */
> > struct {
> > dma_addr_t dma_addr
Adding __packed here will remove the 4 byte hole before the union
and the compiler seems clever enough to know that anything following
a 'long' must also be 'long' aligned.
So you don't get anything horrid like byte accesses.
On 64bit dma_addr will remain 64bit aligned.
On arm32 dma_addr will be 32bit aligned - but forcing two 32bit access
won't make any difference.
So definitely the only simple fix.
David
> > ; /* 8 8 */
> > }; /* 8 8 */
> [...]
> > } __attribute__((__aligned__(8))); /* 8 24 */
> > union {
> > atomic_t _mapcount; /* 32 4 */
> > unsigned int page_type; /* 32 4 */
> > unsigned int active; /* 32 4 */
> > int units; /* 32 4 */
> > }; /* 32 4 */
> > atomic_t _refcount; /* 36 4 */
> >
> > /* size: 40, cachelines: 1, members: 4 */
> > /* sum members: 36, holes: 1, sum holes: 4 */
> > /* forced alignments: 1, forced holes: 1, sum forced holes: 4 */
> > /* last cacheline: 40 bytes */
> > } __attribute__((__aligned__(8)));
>
> If you also enable CONFIG_MEMCG or enough options to make
> LAST_CPUPID_NOT_IN_PAGE_FLAGS true, you'll end up with another 4-byte
> hole at the end.
-
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