[linux-next:master 10742/11059] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1008:5: warning: no previous prototype for function 'gfx_v9_4_2_query_ras_error_count'

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Hi Hawking,

FYI, the error/warning still remains.

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   6145d80cfc62e3ed8f16ff584d6287e6d88b82b9
commit: 6e5095acd86e568a500b6e5ed61b6c33214eafd0 [10742/11059] drm/amdgpu: split gfx callbacks into ras and non-ras ones
config: x86_64-randconfig-a014-20210408 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 56ea2e2fdd691136d5e6631fa0e447173694b82c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=6e5095acd86e568a500b6e5ed61b6c33214eafd0
        git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
        git fetch --no-tags linux-next master
        git checkout 6e5095acd86e568a500b6e5ed61b6c33214eafd0
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1008:5: warning: no previous prototype for function 'gfx_v9_4_2_query_ras_error_count' [-Wmissing-prototypes]
   int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
       ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1008:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
   ^
   static 
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1054:6: warning: no previous prototype for function 'gfx_v9_4_2_reset_ras_error_count' [-Wmissing-prototypes]
   void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
        ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1054:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
   ^
   static 
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1063:5: warning: no previous prototype for function 'gfx_v9_4_2_ras_error_inject' [-Wmissing-prototypes]
   int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
       ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1063:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
   ^
   static 
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1133:6: warning: no previous prototype for function 'gfx_v9_4_2_query_ras_error_status' [-Wmissing-prototypes]
   void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
        ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1133:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
   ^
   static 
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1143:6: warning: no previous prototype for function 'gfx_v9_4_2_reset_ras_error_status' [-Wmissing-prototypes]
   void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
        ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1143:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
   ^
   static 
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1153:6: warning: no previous prototype for function 'gfx_v9_4_2_enable_watchdog_timer' [-Wmissing-prototypes]
   void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
        ^
   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1153:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
   ^
   static 
   6 warnings generated.


vim +/gfx_v9_4_2_query_ras_error_count +1008 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

22616eb5c9b29f Dennis Li              2021-01-26  1007  
22616eb5c9b29f Dennis Li              2021-01-26 @1008  int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
22616eb5c9b29f Dennis Li              2021-01-26  1009  				   void *ras_error_status)
22616eb5c9b29f Dennis Li              2021-01-26  1010  {
22616eb5c9b29f Dennis Li              2021-01-26  1011  	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
22616eb5c9b29f Dennis Li              2021-01-26  1012  	uint32_t sec_count = 0, ded_count = 0;
22616eb5c9b29f Dennis Li              2021-01-26  1013  
22616eb5c9b29f Dennis Li              2021-01-26  1014  	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
22616eb5c9b29f Dennis Li              2021-01-26  1015  		return -EINVAL;
22616eb5c9b29f Dennis Li              2021-01-26  1016  
22616eb5c9b29f Dennis Li              2021-01-26  1017  	err_data->ue_count = 0;
22616eb5c9b29f Dennis Li              2021-01-26  1018  	err_data->ce_count = 0;
22616eb5c9b29f Dennis Li              2021-01-26  1019  
22616eb5c9b29f Dennis Li              2021-01-26  1020  	gfx_v9_4_2_query_sram_edc_count(adev, &sec_count, &ded_count);
22616eb5c9b29f Dennis Li              2021-01-26  1021  	err_data->ce_count += sec_count;
22616eb5c9b29f Dennis Li              2021-01-26  1022  	err_data->ue_count += ded_count;
22616eb5c9b29f Dennis Li              2021-01-26  1023  
22616eb5c9b29f Dennis Li              2021-01-26  1024  	gfx_v9_4_2_query_utc_edc_count(adev, &sec_count, &ded_count);
22616eb5c9b29f Dennis Li              2021-01-26  1025  	err_data->ce_count += sec_count;
22616eb5c9b29f Dennis Li              2021-01-26  1026  	err_data->ue_count += ded_count;
22616eb5c9b29f Dennis Li              2021-01-26  1027  
22616eb5c9b29f Dennis Li              2021-01-26  1028  	return 0;
22616eb5c9b29f Dennis Li              2021-01-26  1029  }
22616eb5c9b29f Dennis Li              2021-01-26  1030  
22616eb5c9b29f Dennis Li              2021-01-26  1031  static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1032  {
22616eb5c9b29f Dennis Li              2021-01-26  1033  	WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
22616eb5c9b29f Dennis Li              2021-01-26  1034  	WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
22616eb5c9b29f Dennis Li              2021-01-26  1035  	WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
22616eb5c9b29f Dennis Li              2021-01-26  1036  }
22616eb5c9b29f Dennis Li              2021-01-26  1037  
22616eb5c9b29f Dennis Li              2021-01-26  1038  static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1039  {
22616eb5c9b29f Dennis Li              2021-01-26  1040  	uint32_t i, j;
22616eb5c9b29f Dennis Li              2021-01-26  1041  
22616eb5c9b29f Dennis Li              2021-01-26  1042  	mutex_lock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1043  	for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
22616eb5c9b29f Dennis Li              2021-01-26  1044  		for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
22616eb5c9b29f Dennis Li              2021-01-26  1045  		     j++) {
22616eb5c9b29f Dennis Li              2021-01-26  1046  			gfx_v9_4_2_select_se_sh(adev, i, 0, j);
22616eb5c9b29f Dennis Li              2021-01-26  1047  			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
22616eb5c9b29f Dennis Li              2021-01-26  1048  		}
22616eb5c9b29f Dennis Li              2021-01-26  1049  	}
22616eb5c9b29f Dennis Li              2021-01-26  1050  	gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
22616eb5c9b29f Dennis Li              2021-01-26  1051  	mutex_unlock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1052  }
22616eb5c9b29f Dennis Li              2021-01-26  1053  
22616eb5c9b29f Dennis Li              2021-01-26 @1054  void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1055  {
22616eb5c9b29f Dennis Li              2021-01-26  1056  	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
22616eb5c9b29f Dennis Li              2021-01-26  1057  		return;
22616eb5c9b29f Dennis Li              2021-01-26  1058  
22616eb5c9b29f Dennis Li              2021-01-26  1059  	gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL);
22616eb5c9b29f Dennis Li              2021-01-26  1060  	gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL);
22616eb5c9b29f Dennis Li              2021-01-26  1061  }
22616eb5c9b29f Dennis Li              2021-01-26  1062  
22616eb5c9b29f Dennis Li              2021-01-26 @1063  int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
22616eb5c9b29f Dennis Li              2021-01-26  1064  {
22616eb5c9b29f Dennis Li              2021-01-26  1065  	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
22616eb5c9b29f Dennis Li              2021-01-26  1066  	int ret;
22616eb5c9b29f Dennis Li              2021-01-26  1067  	struct ta_ras_trigger_error_input block_info = { 0 };
22616eb5c9b29f Dennis Li              2021-01-26  1068  
22616eb5c9b29f Dennis Li              2021-01-26  1069  	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
22616eb5c9b29f Dennis Li              2021-01-26  1070  		return -EINVAL;
22616eb5c9b29f Dennis Li              2021-01-26  1071  
22616eb5c9b29f Dennis Li              2021-01-26  1072  	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
22616eb5c9b29f Dennis Li              2021-01-26  1073  	block_info.sub_block_index = info->head.sub_block_index;
22616eb5c9b29f Dennis Li              2021-01-26  1074  	block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
22616eb5c9b29f Dennis Li              2021-01-26  1075  	block_info.address = info->address;
22616eb5c9b29f Dennis Li              2021-01-26  1076  	block_info.value = info->value;
22616eb5c9b29f Dennis Li              2021-01-26  1077  
22616eb5c9b29f Dennis Li              2021-01-26  1078  	mutex_lock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1079  	ret = psp_ras_trigger_error(&adev->psp, &block_info);
22616eb5c9b29f Dennis Li              2021-01-26  1080  	mutex_unlock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1081  
22616eb5c9b29f Dennis Li              2021-01-26  1082  	return ret;
22616eb5c9b29f Dennis Li              2021-01-26  1083  }
22616eb5c9b29f Dennis Li              2021-01-26  1084  
22616eb5c9b29f Dennis Li              2021-01-26  1085  static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1086  {
22616eb5c9b29f Dennis Li              2021-01-26  1087  	uint32_t i, j;
22616eb5c9b29f Dennis Li              2021-01-26  1088  	uint32_t reg_value;
22616eb5c9b29f Dennis Li              2021-01-26  1089  
22616eb5c9b29f Dennis Li              2021-01-26  1090  	mutex_lock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1091  
22616eb5c9b29f Dennis Li              2021-01-26  1092  	for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
22616eb5c9b29f Dennis Li              2021-01-26  1093  		for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
22616eb5c9b29f Dennis Li              2021-01-26  1094  		     j++) {
22616eb5c9b29f Dennis Li              2021-01-26  1095  			gfx_v9_4_2_select_se_sh(adev, i, 0, j);
22616eb5c9b29f Dennis Li              2021-01-26  1096  			reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
22616eb5c9b29f Dennis Li              2021-01-26  1097  				gfx_v9_4_2_rdrsp_status_regs));
22616eb5c9b29f Dennis Li              2021-01-26  1098  			if (reg_value)
22616eb5c9b29f Dennis Li              2021-01-26  1099  				dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
22616eb5c9b29f Dennis Li              2021-01-26  1100  						j, reg_value);
761d86d37f86eb Dennis Li              2021-02-04  1101  			/* clear after read */
761d86d37f86eb Dennis Li              2021-02-04  1102  			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
22616eb5c9b29f Dennis Li              2021-01-26  1103  		}
22616eb5c9b29f Dennis Li              2021-01-26  1104  	}
22616eb5c9b29f Dennis Li              2021-01-26  1105  
22616eb5c9b29f Dennis Li              2021-01-26  1106  	gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
22616eb5c9b29f Dennis Li              2021-01-26  1107  	mutex_unlock(&adev->grbm_idx_mutex);
22616eb5c9b29f Dennis Li              2021-01-26  1108  }
22616eb5c9b29f Dennis Li              2021-01-26  1109  
22616eb5c9b29f Dennis Li              2021-01-26  1110  static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1111  {
22616eb5c9b29f Dennis Li              2021-01-26  1112  	uint32_t data;
22616eb5c9b29f Dennis Li              2021-01-26  1113  
22616eb5c9b29f Dennis Li              2021-01-26  1114  	data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);
761d86d37f86eb Dennis Li              2021-02-04  1115  	if (!data) {
22616eb5c9b29f Dennis Li              2021-01-26  1116  		dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
761d86d37f86eb Dennis Li              2021-02-04  1117  		WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
761d86d37f86eb Dennis Li              2021-02-04  1118  	}
22616eb5c9b29f Dennis Li              2021-01-26  1119  
22616eb5c9b29f Dennis Li              2021-01-26  1120  	data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);
761d86d37f86eb Dennis Li              2021-02-04  1121  	if (!data) {
22616eb5c9b29f Dennis Li              2021-01-26  1122  		dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
761d86d37f86eb Dennis Li              2021-02-04  1123  		WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
761d86d37f86eb Dennis Li              2021-02-04  1124  	}
22616eb5c9b29f Dennis Li              2021-01-26  1125  
22616eb5c9b29f Dennis Li              2021-01-26  1126  	data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);
761d86d37f86eb Dennis Li              2021-02-04  1127  	if (!data) {
22616eb5c9b29f Dennis Li              2021-01-26  1128  		dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
761d86d37f86eb Dennis Li              2021-02-04  1129  		WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
761d86d37f86eb Dennis Li              2021-02-04  1130  	}
22616eb5c9b29f Dennis Li              2021-01-26  1131  }
22616eb5c9b29f Dennis Li              2021-01-26  1132  
22616eb5c9b29f Dennis Li              2021-01-26 @1133  void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
22616eb5c9b29f Dennis Li              2021-01-26  1134  {
22616eb5c9b29f Dennis Li              2021-01-26  1135  	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
22616eb5c9b29f Dennis Li              2021-01-26  1136  		return;
22616eb5c9b29f Dennis Li              2021-01-26  1137  
22616eb5c9b29f Dennis Li              2021-01-26  1138  	gfx_v9_4_2_query_ea_err_status(adev);
22616eb5c9b29f Dennis Li              2021-01-26  1139  	gfx_v9_4_2_query_utc_err_status(adev);
761d86d37f86eb Dennis Li              2021-02-04  1140  	gfx_v9_4_2_query_sq_timeout_status(adev);
761d86d37f86eb Dennis Li              2021-02-04  1141  }
761d86d37f86eb Dennis Li              2021-02-04  1142  
761d86d37f86eb Dennis Li              2021-02-04 @1143  void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
761d86d37f86eb Dennis Li              2021-02-04  1144  {
761d86d37f86eb Dennis Li              2021-02-04  1145  	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
761d86d37f86eb Dennis Li              2021-02-04  1146  		return;
761d86d37f86eb Dennis Li              2021-02-04  1147  
761d86d37f86eb Dennis Li              2021-02-04  1148  	gfx_v9_4_2_reset_utc_err_status(adev);
761d86d37f86eb Dennis Li              2021-02-04  1149  	gfx_v9_4_2_reset_ea_err_status(adev);
761d86d37f86eb Dennis Li              2021-02-04  1150  	gfx_v9_4_2_reset_sq_timeout_status(adev);
22616eb5c9b29f Dennis Li              2021-01-26  1151  }
88f8575bca5fc7 Dennis Li              2021-03-05  1152  
88f8575bca5fc7 Dennis Li              2021-03-05 @1153  void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
88f8575bca5fc7 Dennis Li              2021-03-05  1154  {
88f8575bca5fc7 Dennis Li              2021-03-05  1155  	uint32_t i;
88f8575bca5fc7 Dennis Li              2021-03-05  1156  	uint32_t data;
88f8575bca5fc7 Dennis Li              2021-03-05  1157  
88f8575bca5fc7 Dennis Li              2021-03-05  1158  	data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
88f8575bca5fc7 Dennis Li              2021-03-05  1159  			     amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
88f8575bca5fc7 Dennis Li              2021-03-05  1160  									   0);
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1161  
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1162  	if (amdgpu_watchdog_timer.timeout_fatal_disable &&
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1163  	    (amdgpu_watchdog_timer.period < 1 ||
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1164  	     amdgpu_watchdog_timer.period > 0x23)) {
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1165  		dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1166  		amdgpu_watchdog_timer.period = 0x23;
4464820dc7edd2 Harish Kasiviswanathan 2021-02-23  1167  	}
88f8575bca5fc7 Dennis Li              2021-03-05  1168  	data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
88f8575bca5fc7 Dennis Li              2021-03-05  1169  			     amdgpu_watchdog_timer.period);
88f8575bca5fc7 Dennis Li              2021-03-05  1170  
88f8575bca5fc7 Dennis Li              2021-03-05  1171  	mutex_lock(&adev->grbm_idx_mutex);
88f8575bca5fc7 Dennis Li              2021-03-05  1172  	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
88f8575bca5fc7 Dennis Li              2021-03-05  1173  		gfx_v9_4_2_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
88f8575bca5fc7 Dennis Li              2021-03-05  1174  		WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data);
88f8575bca5fc7 Dennis Li              2021-03-05  1175  	}
88f8575bca5fc7 Dennis Li              2021-03-05  1176  	gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
88f8575bca5fc7 Dennis Li              2021-03-05  1177  	mutex_unlock(&adev->grbm_idx_mutex);
88f8575bca5fc7 Dennis Li              2021-03-05  1178  }
88f8575bca5fc7 Dennis Li              2021-03-05  1179  

:::::: The code at line 1008 was first introduced by commit
:::::: 22616eb5c9b29fca2361d5bd8339efafddee7809 drm/amdgpu: add ras support for gfx of aldebaran

:::::: TO: Dennis Li <Dennis.Li@xxxxxxx>
:::::: CC: Alex Deucher <alexander.deucher@xxxxxxx>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip


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