On 14 Mar 2021, at 20:03, Yu Zhao wrote: > On Sun, Mar 14, 2021 at 10:51:03PM +0000, Matthew Wilcox wrote: >> On Sun, Mar 14, 2021 at 06:12:42PM -0400, Zi Yan wrote: >>> On 13 Mar 2021, at 2:57, Yu Zhao wrote: >>> >>>> Some architectures support the accessed bit on non-leaf PMD entries >>>> (parents) in addition to leaf PTE entries (children) where pages are >>>> mapped, e.g., x86_64 sets the accessed bit on a parent when using it >>>> as part of linear-address translation [1]. Page table walkers who are >>>> interested in the accessed bit on children can take advantage of this: >>>> they do not need to search the children when the accessed bit is not >>>> set on a parent, given that they have previously cleared the accessed >>>> bit on this parent in addition to its children. >>>> >>>> [1]: Intel 64 and IA-32 Architectures Software Developer's Manual >>>> Volume 3 (October 2019), section 4.8 >>> >>> Just curious. Does this also apply to non-leaf PUD entries? Do you >>> mind sharing which sentence from the manual gives the information? >> >> The first few sentences from 4.8: >> >> : For any paging-structure entry that is used during linear-address >> : translation, bit 5 is the accessed flag. For paging-structure >> : entries that map a page (as opposed to referencing another paging >> : structure), bit 6 is the dirty flag. These flags are provided for >> : use by memory-management software to manage the transfer of pages and >> : paging structures into and out of physical memory. >> >> : Whenever the processor uses a paging-structure entry as part of >> : linear-address translation, it sets the accessed flag in that entry >> : (if it is not already set). Matthew, thanks for the pointer. > > As far as I know x86 is the one that supports this. > >> The way they differentiate between the A and D bits makes it clear to >> me that the A bit is set at each level of the tree, but the D bit is >> only set on leaf entries. > > And the difference makes perfect sense (to me). Kudos to Intel. Hi Yu, You only introduced HAVE_ARCH_PARENT_PMD_YOUNG but no HAVE_ARCH_PARENT_PUD_YOUNG. Is it PUD granularity too large to be useful for multigenerational LRU algorithm? Thanks. — Best Regards, Yan Zi
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