On 3/12/21 11:57 PM, Yu Zhao wrote: > Some architectures support the accessed bit on non-leaf PMD entries > (parents) in addition to leaf PTE entries (children) where pages are > mapped, e.g., x86_64 sets the accessed bit on a parent when using it > as part of linear-address translation [1]. Page table walkers who are > interested in the accessed bit on children can take advantage of this: > they do not need to search the children when the accessed bit is not > set on a parent, given that they have previously cleared the accessed > bit on this parent in addition to its children. I'd like to hear a *LOT* more about how this is going to be used. The one part of this which is entirely missing is the interaction with the TLB and mid-level paging structure caches. The CPU is pretty aggressive about setting no-leaf accessed bits when TLB entries are created. This *looks* to be depending on that behavior, but it would be nice to spell it out explicitly.
