On Fri, Feb 05, 2021 at 07:01:27PM +0300, Kirill A. Shutemov wrote: > On Fri, Feb 05, 2021 at 04:49:05PM +0100, Peter Zijlstra wrote: > > On Fri, Feb 05, 2021 at 06:16:20PM +0300, Kirill A. Shutemov wrote: > > > The feature competes for bits with 5-level paging: LAM_U48 makes it > > > impossible to map anything about 47-bits. The patchset made these > > > capability mutually exclusive: whatever used first wins. LAM_U57 can be > > > combined with mappings above 47-bits. > > > > And I suppose we still can't switch between 4 and 5 level at runtime, > > using a CR3 bit? > > No. And I can't imagine how would it work with 5-level on kernel side. KPTI already switches CR3 on every entry and only maps a very limited number of kernel pages in the user map. This means a 4 level user page-table should be possible. The kernel page-tables would only need to update their p5d[0] on every 4l user change. Not as nice as actually having separate user and kernel page-tables in hardware, but it would actually make 5l page-tables useful on machines with less than stupid amounds of memory I think. One of the road-blocks to doing per-cpu kernel page-tables is having to do 2k copies, only having to update a single P5D entry would be ideal. Ofcourse, once we get 5l user tables we're back to being stupid, but maybe tasks with that much memory don't actually switch much, who knows.
