On 1/28/21 2:49 AM, Saravanan D wrote: > +++ b/Documentation/admin-guide/mm/direct_mapping_splits.rst > @@ -0,0 +1,59 @@ > +.. SPDX-License-Identifier: GPL-2.0 > + > +===================== > +Direct Mapping Splits > +===================== > + > +Kernel maps all of physical memory in linear/direct mapped pages with > +translation of virtual kernel address to physical address is achieved > +through a simple subtraction of offset. CPUs maintain a cache of these > +translations on fast caches called TLBs. CPU architectures like x86 allow > +direct mapping large portions of memory into hugepages (2M, 1G, etc) in > +various page table levels. > + > +Maintaining huge direct mapped pages greatly reduces TLB miss pressure. > +The splintering of huge direct pages into smaller ones does result in > +a measurable performance hit caused by frequent TLB miss and reloads. Eek. There really doesn't appear to be a place in Documentation/ that we've documented vmstat entries. Maybe you can start: Documentation/admin-guide/mm/vmstat.rst Also, I don't think we need background on the direct map or TLBs here. Just get to the point and describe what the files do, don't justify why they are there. I also agree with Willy that you should qualify some of the strong statements (if they remain) in your changelog and documentation> This: Maintaining huge direct mapped pages greatly reduces TLB miss pressure. for instance isn't universally true. There were CPUs with a very small number of 1G TLB entries. Using 1G pages on those systems often led to *GREATER* TLB pressure and lower performance.
