> On Nov 23, 2020, at 1:25 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > > On Mon, Nov 23 2020 at 22:15, Thomas Gleixner wrote: >>> On Sun, Nov 22 2020 at 15:16, Andy Lutomirski wrote: >>>> On Fri, Nov 20, 2020 at 1:29 AM Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: >>> The common case of a CPU switching back and forth between a small >>> number of mms would have no significant overhead. >> >> For CPUs which do not support PCID this sucks, which is everything pre >> Westmere and all of 32bit. Yes, 32bit. If we go there then 32bit has to >> bite the bullet and use the very same mechanism. Not that I care much >> TBH. > > Bah, I completely forgot that AMD does not support PCID before Zen3 > which is a major showstopper. Why? Couldn’t we rig up the code so we still track all the ASIDs even if there is no CPU support? We would take the TLB flush hit on every context switch, but we pay that cost anyway. We would avoid the extra copy in the same cases in which we would avoid it if we had PCID. > > Thanks, > > tglx
