[linux-next:master 3872/4770] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:482:5: warning: no previous prototype for function 'amdgpu_info_ioctl'

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   2ad4382198191b634e69a370d041928484ef0bf8
commit: 5088d6572e8ff6c25433858a4e701aa0fd9364c0 [3872/4770] drm/amdgpu: Make struct drm_driver const
config: x86_64-randconfig-a015-20201109 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 09ec07827b1128504457a93dee80b2ceee1af600)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=5088d6572e8ff6c25433858a4e701aa0fd9364c0
        git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
        git fetch --no-tags linux-next master
        git checkout 5088d6572e8ff6c25433858a4e701aa0fd9364c0
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:482:5: warning: no previous prototype for function 'amdgpu_info_ioctl' [-Wmissing-prototypes]
   int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
       ^
   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:482:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
   ^
   static 
   1 warning generated.

vim +/amdgpu_info_ioctl +482 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   466	
   467	/*
   468	 * Userspace get information ioctl
   469	 */
   470	/**
   471	 * amdgpu_info_ioctl - answer a device specific request.
   472	 *
   473	 * @adev: amdgpu device pointer
   474	 * @data: request object
   475	 * @filp: drm filp
   476	 *
   477	 * This function is used to pass device specific parameters to the userspace
   478	 * drivers.  Examples include: pci device id, pipeline parms, tiling params,
   479	 * etc. (all asics).
   480	 * Returns 0 on success, -EINVAL on failure.
   481	 */
 > 482	int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
   483	{
   484		struct amdgpu_device *adev = drm_to_adev(dev);
   485		struct drm_amdgpu_info *info = data;
   486		struct amdgpu_mode_info *minfo = &adev->mode_info;
   487		void __user *out = (void __user *)(uintptr_t)info->return_pointer;
   488		uint32_t size = info->return_size;
   489		struct drm_crtc *crtc;
   490		uint32_t ui32 = 0;
   491		uint64_t ui64 = 0;
   492		int i, found;
   493		int ui32_size = sizeof(ui32);
   494	
   495		if (!info->return_size || !info->return_pointer)
   496			return -EINVAL;
   497	
   498		switch (info->query) {
   499		case AMDGPU_INFO_ACCEL_WORKING:
   500			ui32 = adev->accel_working;
   501			return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
   502		case AMDGPU_INFO_CRTC_FROM_ID:
   503			for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
   504				crtc = (struct drm_crtc *)minfo->crtcs[i];
   505				if (crtc && crtc->base.id == info->mode_crtc.id) {
   506					struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
   507					ui32 = amdgpu_crtc->crtc_id;
   508					found = 1;
   509					break;
   510				}
   511			}
   512			if (!found) {
   513				DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
   514				return -EINVAL;
   515			}
   516			return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
   517		case AMDGPU_INFO_HW_IP_INFO: {
   518			struct drm_amdgpu_info_hw_ip ip = {};
   519			int ret;
   520	
   521			ret = amdgpu_hw_ip_info(adev, info, &ip);
   522			if (ret)
   523				return ret;
   524	
   525			ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
   526			return ret ? -EFAULT : 0;
   527		}
   528		case AMDGPU_INFO_HW_IP_COUNT: {
   529			enum amd_ip_block_type type;
   530			uint32_t count = 0;
   531	
   532			switch (info->query_hw_ip.type) {
   533			case AMDGPU_HW_IP_GFX:
   534				type = AMD_IP_BLOCK_TYPE_GFX;
   535				break;
   536			case AMDGPU_HW_IP_COMPUTE:
   537				type = AMD_IP_BLOCK_TYPE_GFX;
   538				break;
   539			case AMDGPU_HW_IP_DMA:
   540				type = AMD_IP_BLOCK_TYPE_SDMA;
   541				break;
   542			case AMDGPU_HW_IP_UVD:
   543				type = AMD_IP_BLOCK_TYPE_UVD;
   544				break;
   545			case AMDGPU_HW_IP_VCE:
   546				type = AMD_IP_BLOCK_TYPE_VCE;
   547				break;
   548			case AMDGPU_HW_IP_UVD_ENC:
   549				type = AMD_IP_BLOCK_TYPE_UVD;
   550				break;
   551			case AMDGPU_HW_IP_VCN_DEC:
   552			case AMDGPU_HW_IP_VCN_ENC:
   553				type = AMD_IP_BLOCK_TYPE_VCN;
   554				break;
   555			case AMDGPU_HW_IP_VCN_JPEG:
   556				type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
   557					AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
   558				break;
   559			default:
   560				return -EINVAL;
   561			}
   562	
   563			for (i = 0; i < adev->num_ip_blocks; i++)
   564				if (adev->ip_blocks[i].version->type == type &&
   565				    adev->ip_blocks[i].status.valid &&
   566				    count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
   567					count++;
   568	
   569			return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
   570		}
   571		case AMDGPU_INFO_TIMESTAMP:
   572			ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
   573			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   574		case AMDGPU_INFO_FW_VERSION: {
   575			struct drm_amdgpu_info_firmware fw_info;
   576			int ret;
   577	
   578			/* We only support one instance of each IP block right now. */
   579			if (info->query_fw.ip_instance != 0)
   580				return -EINVAL;
   581	
   582			ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
   583			if (ret)
   584				return ret;
   585	
   586			return copy_to_user(out, &fw_info,
   587					    min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
   588		}
   589		case AMDGPU_INFO_NUM_BYTES_MOVED:
   590			ui64 = atomic64_read(&adev->num_bytes_moved);
   591			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   592		case AMDGPU_INFO_NUM_EVICTIONS:
   593			ui64 = atomic64_read(&adev->num_evictions);
   594			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   595		case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
   596			ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
   597			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   598		case AMDGPU_INFO_VRAM_USAGE:
   599			ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
   600			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   601		case AMDGPU_INFO_VIS_VRAM_USAGE:
   602			ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
   603			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   604		case AMDGPU_INFO_GTT_USAGE:
   605			ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
   606			return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
   607		case AMDGPU_INFO_GDS_CONFIG: {
   608			struct drm_amdgpu_info_gds gds_info;
   609	
   610			memset(&gds_info, 0, sizeof(gds_info));
   611			gds_info.compute_partition_size = adev->gds.gds_size;
   612			gds_info.gds_total_size = adev->gds.gds_size;
   613			gds_info.gws_per_compute_partition = adev->gds.gws_size;
   614			gds_info.oa_per_compute_partition = adev->gds.oa_size;
   615			return copy_to_user(out, &gds_info,
   616					    min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
   617		}
   618		case AMDGPU_INFO_VRAM_GTT: {
   619			struct drm_amdgpu_info_vram_gtt vram_gtt;
   620	
   621			vram_gtt.vram_size = adev->gmc.real_vram_size -
   622				atomic64_read(&adev->vram_pin_size) -
   623				AMDGPU_VM_RESERVED_VRAM;
   624			vram_gtt.vram_cpu_accessible_size =
   625				min(adev->gmc.visible_vram_size -
   626				    atomic64_read(&adev->visible_pin_size),
   627				    vram_gtt.vram_size);
   628			vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
   629			vram_gtt.gtt_size *= PAGE_SIZE;
   630			vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
   631			return copy_to_user(out, &vram_gtt,
   632					    min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
   633		}
   634		case AMDGPU_INFO_MEMORY: {
   635			struct drm_amdgpu_memory_info mem;
   636			struct ttm_resource_manager *vram_man =
   637				ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
   638			struct ttm_resource_manager *gtt_man =
   639				ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
   640			memset(&mem, 0, sizeof(mem));
   641			mem.vram.total_heap_size = adev->gmc.real_vram_size;
   642			mem.vram.usable_heap_size = adev->gmc.real_vram_size -
   643				atomic64_read(&adev->vram_pin_size) -
   644				AMDGPU_VM_RESERVED_VRAM;
   645			mem.vram.heap_usage =
   646				amdgpu_vram_mgr_usage(vram_man);
   647			mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
   648	
   649			mem.cpu_accessible_vram.total_heap_size =
   650				adev->gmc.visible_vram_size;
   651			mem.cpu_accessible_vram.usable_heap_size =
   652				min(adev->gmc.visible_vram_size -
   653				    atomic64_read(&adev->visible_pin_size),
   654				    mem.vram.usable_heap_size);
   655			mem.cpu_accessible_vram.heap_usage =
   656				amdgpu_vram_mgr_vis_usage(vram_man);
   657			mem.cpu_accessible_vram.max_allocation =
   658				mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
   659	
   660			mem.gtt.total_heap_size = gtt_man->size;
   661			mem.gtt.total_heap_size *= PAGE_SIZE;
   662			mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
   663				atomic64_read(&adev->gart_pin_size);
   664			mem.gtt.heap_usage =
   665				amdgpu_gtt_mgr_usage(gtt_man);
   666			mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
   667	
   668			return copy_to_user(out, &mem,
   669					    min((size_t)size, sizeof(mem)))
   670					    ? -EFAULT : 0;
   671		}
   672		case AMDGPU_INFO_READ_MMR_REG: {
   673			unsigned n, alloc_size;
   674			uint32_t *regs;
   675			unsigned se_num = (info->read_mmr_reg.instance >>
   676					   AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
   677					  AMDGPU_INFO_MMR_SE_INDEX_MASK;
   678			unsigned sh_num = (info->read_mmr_reg.instance >>
   679					   AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
   680					  AMDGPU_INFO_MMR_SH_INDEX_MASK;
   681	
   682			/* set full masks if the userspace set all bits
   683			 * in the bitfields */
   684			if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
   685				se_num = 0xffffffff;
   686			else if (se_num >= AMDGPU_GFX_MAX_SE)
   687				return -EINVAL;
   688			if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
   689				sh_num = 0xffffffff;
   690			else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
   691				return -EINVAL;
   692	
   693			if (info->read_mmr_reg.count > 128)
   694				return -EINVAL;
   695	
   696			regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
   697			if (!regs)
   698				return -ENOMEM;
   699			alloc_size = info->read_mmr_reg.count * sizeof(*regs);
   700	
   701			amdgpu_gfx_off_ctrl(adev, false);
   702			for (i = 0; i < info->read_mmr_reg.count; i++) {
   703				if (amdgpu_asic_read_register(adev, se_num, sh_num,
   704							      info->read_mmr_reg.dword_offset + i,
   705							      &regs[i])) {
   706					DRM_DEBUG_KMS("unallowed offset %#x\n",
   707						      info->read_mmr_reg.dword_offset + i);
   708					kfree(regs);
   709					amdgpu_gfx_off_ctrl(adev, true);
   710					return -EFAULT;
   711				}
   712			}
   713			amdgpu_gfx_off_ctrl(adev, true);
   714			n = copy_to_user(out, regs, min(size, alloc_size));
   715			kfree(regs);
   716			return n ? -EFAULT : 0;
   717		}
   718		case AMDGPU_INFO_DEV_INFO: {
   719			struct drm_amdgpu_info_device dev_info;
   720			uint64_t vm_size;
   721	
   722			memset(&dev_info, 0, sizeof(dev_info));
   723			dev_info.device_id = dev->pdev->device;
   724			dev_info.chip_rev = adev->rev_id;
   725			dev_info.external_rev = adev->external_rev_id;
   726			dev_info.pci_rev = dev->pdev->revision;
   727			dev_info.family = adev->family;
   728			dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
   729			dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
   730			/* return all clocks in KHz */
   731			dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
   732			if (adev->pm.dpm_enabled) {
   733				dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
   734				dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
   735			} else {
   736				dev_info.max_engine_clock = adev->clock.default_sclk * 10;
   737				dev_info.max_memory_clock = adev->clock.default_mclk * 10;
   738			}
   739			dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
   740			dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
   741				adev->gfx.config.max_shader_engines;
   742			dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
   743			dev_info._pad = 0;
   744			dev_info.ids_flags = 0;
   745			if (adev->flags & AMD_IS_APU)
   746				dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
   747			if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
   748				dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
   749			if (amdgpu_is_tmz(adev))
   750				dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
   751	
   752			vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
   753			vm_size -= AMDGPU_VA_RESERVED_SIZE;
   754	
   755			/* Older VCE FW versions are buggy and can handle only 40bits */
   756			if (adev->vce.fw_version &&
   757			    adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
   758				vm_size = min(vm_size, 1ULL << 40);
   759	
   760			dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
   761			dev_info.virtual_address_max =
   762				min(vm_size, AMDGPU_GMC_HOLE_START);
   763	
   764			if (vm_size > AMDGPU_GMC_HOLE_START) {
   765				dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
   766				dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
   767			}
   768			dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
   769			dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
   770			dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
   771			dev_info.cu_active_number = adev->gfx.cu_info.number;
   772			dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
   773			dev_info.ce_ram_size = adev->gfx.ce_ram_size;
   774			memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
   775			       sizeof(adev->gfx.cu_info.ao_cu_bitmap));
   776			memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
   777			       sizeof(adev->gfx.cu_info.bitmap));
   778			dev_info.vram_type = adev->gmc.vram_type;
   779			dev_info.vram_bit_width = adev->gmc.vram_width;
   780			dev_info.vce_harvest_config = adev->vce.harvest_config;
   781			dev_info.gc_double_offchip_lds_buf =
   782				adev->gfx.config.double_offchip_lds_buf;
   783			dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
   784			dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
   785			dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
   786			dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
   787			dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
   788			dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
   789			dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
   790	
   791			if (adev->family >= AMDGPU_FAMILY_NV)
   792				dev_info.pa_sc_tile_steering_override =
   793					adev->gfx.config.pa_sc_tile_steering_override;
   794	
   795			dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
   796	
   797			return copy_to_user(out, &dev_info,
   798					    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
   799		}
   800		case AMDGPU_INFO_VCE_CLOCK_TABLE: {
   801			unsigned i;
   802			struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
   803			struct amd_vce_state *vce_state;
   804	
   805			for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
   806				vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
   807				if (vce_state) {
   808					vce_clk_table.entries[i].sclk = vce_state->sclk;
   809					vce_clk_table.entries[i].mclk = vce_state->mclk;
   810					vce_clk_table.entries[i].eclk = vce_state->evclk;
   811					vce_clk_table.num_valid_entries++;
   812				}
   813			}
   814	
   815			return copy_to_user(out, &vce_clk_table,
   816					    min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
   817		}
   818		case AMDGPU_INFO_VBIOS: {
   819			uint32_t bios_size = adev->bios_size;
   820	
   821			switch (info->vbios_info.type) {
   822			case AMDGPU_INFO_VBIOS_SIZE:
   823				return copy_to_user(out, &bios_size,
   824						min((size_t)size, sizeof(bios_size)))
   825						? -EFAULT : 0;
   826			case AMDGPU_INFO_VBIOS_IMAGE: {
   827				uint8_t *bios;
   828				uint32_t bios_offset = info->vbios_info.offset;
   829	
   830				if (bios_offset >= bios_size)
   831					return -EINVAL;
   832	
   833				bios = adev->bios + bios_offset;
   834				return copy_to_user(out, bios,
   835						    min((size_t)size, (size_t)(bios_size - bios_offset)))
   836						? -EFAULT : 0;
   837			}
   838			default:
   839				DRM_DEBUG_KMS("Invalid request %d\n",
   840						info->vbios_info.type);
   841				return -EINVAL;
   842			}
   843		}
   844		case AMDGPU_INFO_NUM_HANDLES: {
   845			struct drm_amdgpu_info_num_handles handle;
   846	
   847			switch (info->query_hw_ip.type) {
   848			case AMDGPU_HW_IP_UVD:
   849				/* Starting Polaris, we support unlimited UVD handles */
   850				if (adev->asic_type < CHIP_POLARIS10) {
   851					handle.uvd_max_handles = adev->uvd.max_handles;
   852					handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
   853	
   854					return copy_to_user(out, &handle,
   855						min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
   856				} else {
   857					return -ENODATA;
   858				}
   859	
   860				break;
   861			default:
   862				return -EINVAL;
   863			}
   864		}
   865		case AMDGPU_INFO_SENSOR: {
   866			if (!adev->pm.dpm_enabled)
   867				return -ENOENT;
   868	
   869			switch (info->sensor_info.type) {
   870			case AMDGPU_INFO_SENSOR_GFX_SCLK:
   871				/* get sclk in Mhz */
   872				if (amdgpu_dpm_read_sensor(adev,
   873							   AMDGPU_PP_SENSOR_GFX_SCLK,
   874							   (void *)&ui32, &ui32_size)) {
   875					return -EINVAL;
   876				}
   877				ui32 /= 100;
   878				break;
   879			case AMDGPU_INFO_SENSOR_GFX_MCLK:
   880				/* get mclk in Mhz */
   881				if (amdgpu_dpm_read_sensor(adev,
   882							   AMDGPU_PP_SENSOR_GFX_MCLK,
   883							   (void *)&ui32, &ui32_size)) {
   884					return -EINVAL;
   885				}
   886				ui32 /= 100;
   887				break;
   888			case AMDGPU_INFO_SENSOR_GPU_TEMP:
   889				/* get temperature in millidegrees C */
   890				if (amdgpu_dpm_read_sensor(adev,
   891							   AMDGPU_PP_SENSOR_GPU_TEMP,
   892							   (void *)&ui32, &ui32_size)) {
   893					return -EINVAL;
   894				}
   895				break;
   896			case AMDGPU_INFO_SENSOR_GPU_LOAD:
   897				/* get GPU load */
   898				if (amdgpu_dpm_read_sensor(adev,
   899							   AMDGPU_PP_SENSOR_GPU_LOAD,
   900							   (void *)&ui32, &ui32_size)) {
   901					return -EINVAL;
   902				}
   903				break;
   904			case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
   905				/* get average GPU power */
   906				if (amdgpu_dpm_read_sensor(adev,
   907							   AMDGPU_PP_SENSOR_GPU_POWER,
   908							   (void *)&ui32, &ui32_size)) {
   909					return -EINVAL;
   910				}
   911				ui32 >>= 8;
   912				break;
   913			case AMDGPU_INFO_SENSOR_VDDNB:
   914				/* get VDDNB in millivolts */
   915				if (amdgpu_dpm_read_sensor(adev,
   916							   AMDGPU_PP_SENSOR_VDDNB,
   917							   (void *)&ui32, &ui32_size)) {
   918					return -EINVAL;
   919				}
   920				break;
   921			case AMDGPU_INFO_SENSOR_VDDGFX:
   922				/* get VDDGFX in millivolts */
   923				if (amdgpu_dpm_read_sensor(adev,
   924							   AMDGPU_PP_SENSOR_VDDGFX,
   925							   (void *)&ui32, &ui32_size)) {
   926					return -EINVAL;
   927				}
   928				break;
   929			case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
   930				/* get stable pstate sclk in Mhz */
   931				if (amdgpu_dpm_read_sensor(adev,
   932							   AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
   933							   (void *)&ui32, &ui32_size)) {
   934					return -EINVAL;
   935				}
   936				ui32 /= 100;
   937				break;
   938			case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
   939				/* get stable pstate mclk in Mhz */
   940				if (amdgpu_dpm_read_sensor(adev,
   941							   AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
   942							   (void *)&ui32, &ui32_size)) {
   943					return -EINVAL;
   944				}
   945				ui32 /= 100;
   946				break;
   947			default:
   948				DRM_DEBUG_KMS("Invalid request %d\n",
   949					      info->sensor_info.type);
   950				return -EINVAL;
   951			}
   952			return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
   953		}
   954		case AMDGPU_INFO_VRAM_LOST_COUNTER:
   955			ui32 = atomic_read(&adev->vram_lost_counter);
   956			return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
   957		case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
   958			struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
   959			uint64_t ras_mask;
   960	
   961			if (!ras)
   962				return -EINVAL;
   963			ras_mask = (uint64_t)ras->supported << 32 | ras->features;
   964	
   965			return copy_to_user(out, &ras_mask,
   966					min_t(u64, size, sizeof(ras_mask))) ?
   967				-EFAULT : 0;
   968		}
   969		default:
   970			DRM_DEBUG_KMS("Invalid request %d\n", info->query);
   971			return -EINVAL;
   972		}
   973		return 0;
   974	}
   975	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip


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