On Fri, Oct 02, 2020 at 01:10:28AM +0200, Andrey Konovalov wrote: > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 23c326a06b2d..6c1a6621d769 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -40,9 +40,15 @@ > #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA > > #ifdef CONFIG_KASAN_SW_TAGS > -#define TCR_KASAN_FLAGS TCR_TBI1 > +#define TCR_KASAN_SW_FLAGS TCR_TBI1 > #else > -#define TCR_KASAN_FLAGS 0 > +#define TCR_KASAN_SW_FLAGS 0 > +#endif > + > +#ifdef CONFIG_KASAN_HW_TAGS > +#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 > +#else > +#define TCR_KASAN_HW_FLAGS 0 > #endif > > /* > @@ -427,6 +433,10 @@ SYM_FUNC_START(__cpu_setup) > */ > mov_q x5, MAIR_EL1_SET > #ifdef CONFIG_ARM64_MTE > + mte_tcr .req x20 > + > + mov mte_tcr, #0 > + > /* > * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported > * (ID_AA64PFR1_EL1[11:8] > 1). > @@ -447,6 +457,9 @@ SYM_FUNC_START(__cpu_setup) > /* clear any pending tag check faults in TFSR*_EL1 */ > msr_s SYS_TFSR_EL1, xzr > msr_s SYS_TFSRE0_EL1, xzr > + > + /* set the TCR_EL1 bits */ > + mov_q mte_tcr, TCR_KASAN_HW_FLAGS > 1: > #endif > msr mair_el1, x5 > @@ -456,7 +469,11 @@ SYM_FUNC_START(__cpu_setup) > */ > mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ > TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ > - TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS > + TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS > +#ifdef CONFIG_ARM64_MTE > + orr x10, x10, mte_tcr > + .unreq mte_tcr > +#endif Don't we miss the TBI1 bit here? I think the v3 version of this patch was better. -- Catalin
