On Sat, Jul 30, 2011 at 8:27 AM, Linus Torvalds
<torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
>
> Do we allocate the page map array sufficiently aligned that we
> actually don't ever have the case of straddling a cacheline? I didn't
> check.
Oh, and another thing worth checking: did somebody actually check the
timings for:
- *just* the alignment change?
IOW, maybe some of the netperf improvement isn't from the lockless
path, but exactly from 'struct page' always being in a single
cacheline?
- check performance with cmpxchg16b *without* the alignment.
Sometimes especially intel is so good at unaligned accesses that
you wouldn't see an issue. Now, locked ops are usually special (and
crossing cachelines with a locked op is dubious at best), so there may
actually be correctness issues involved too, but it would be
interesting to hear if anybody actually just tried it.
Hmm?
Linus
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