On Mon, Apr 20, 2020 at 7:49 PM Al Viro <viro@xxxxxxxxxxxxxxxxxx> wrote:
>
> The only source I'd been able to find speaks of >= 60 cycles
> (and possibly much more) for non-pipelined coprocessor instructions;
> the list of such does contain loads and stores to a bunch of registers.
> However, the register in question (p15/c3) has only store mentioned there,
> so loads might be cheap; no obvious reasons for those to be slow.
> That's a question to arm folks, I'm afraid... rmk?
_If_ it turns out to be expensive, is there any reason we couldn't
just cache the value in general?
That's what x86 tends to do with expensive system registers. One
example would be "msr_misc_features_shadow".
But maybe that's something to worry about when/if it turns out to
actually be a problem?
Linus
