On 2/13/20 8:52 AM, Arnd Bergmann wrote:
On Wed, Feb 12, 2020 at 9:50 AM Russell King - ARM Linux admin
<linux@xxxxxxxxxxxxxxx> wrote:
On Tue, Feb 11, 2020 at 05:03:02PM -0800, Linus Torvalds wrote:
On Tue, Feb 11, 2020 at 4:47 PM Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> wrote:
What's the situation with highmem on ARM?
Afaik it's exactly the same as highmem on x86 - only 32-bit ARM ever
needed it, and I was ranting at some people for repeating all the
mistakes Intel did.
But arm64 doesn't need it, and while 32-bit arm is obviosuly still
selling, I think that in many ways the switch-over to 64-bit has been
quicker on ARM than it was on x86. Partly because it happened later
(so all the 64-bit teething pains were dealt with), but largely
because everybody ended up actively discouraging 32-bit on the Android
side.
There were a couple of unfortunate early 32-bit arm server attempts,
but they were - predictably - complete garbage and nobody bought them.
They don't exist any more.
I'd generally agree with that, the systems with more than 4GB tended to
be high-end systems predating the Cortex-A53/A57 that quickly got
replaced once there were actual 64-bit parts, this would include axm5516
(replaced with x86-64 cores after sale to Intel), hip04 (replaced
with arm64), or ecx-2000 (Calxeda bankruptcy).
The one 32-bit SoC that I can think of that can actually drive lots of
RAM and is still actively marketed is TI Keystone-2/AM5K2.
The embedded AM5K2 is listed supporting up to 8GB of RAM, but
the verison in the HPE ProLiant m800 server could take up to 32GB (!).
I added Santosh and Kishon to Cc, they can probably comment on how
long they think users will upgrade kernels on these. I suspect these
devices can live for a very long time in things like wireless base stations,
but it's possible that they all run on old kernels anyway by now (and are
not worried about y2038).
So at least my gut feel is that the arm people don't have any big
reason to push for maintaining HIGHMEM support either.
But I'm adding a couple of arm people and the arm list just in case
they have some input.
The Keystone generations of SOCs have been used in different areas and
they will be used for long unless says otherwise.
Apart from just split of lowmem and highmem, one of the peculiar thing
with Keystome family of SOCs is the DDR is addressable from two
addressing ranges. The lowmem address range is actually non-cached
range and the higher range is the cacheable.
So apart from LPAE, another change I needed to do back then is to boot
the linux from lowmem with bootstrap MMU tables and then re-create
MMU tables early (mmu init) and use higher range for entire memory so
that L3 cache can be used.
AFAIK, all the derived SOCs from Keystone architecture inherently
use this feature.
Regards,
Santosh
