On Fri, 3 Jan 2020 13:18:59 +0100 Brice Goglin <brice.goglin@xxxxxxxxx> wrote: > Le 03/01/2020 à 11:09, Jonathan Cameron a écrit : > > > > 1) If the memory and processor are in the same domain, that should mean the > > access characteristics within that domain are the best in the system. > > It is possible to have a setup with very low latency access > > from a particular processor but also low bandwidth. Another domain may have > > high bandwidth but long latency. Such systems may occur, but they are probably > > going to not be for 'normal memory the OS can just use'. > > > > 2) If we have a relevant "Memory Proximity Domain Attributes Structure" > > Note this was renamed in acpi 6.3 from "Address Range Structure" as > > it no longer has any address ranges. > > (which are entirely optional btw) that indicates that the memory controller > > for a given memory lies in the proximity domain of the Initiator specified. > > If that happens we ignore cases where hmat says somewhere else is nearer > > via bandwidth and latency. > > > > For case 1) I'm not sure we actually enforce it. > > I think you've hit case 2). > > > > Removing the address range structures should work, or as you say you can > > move that memory into separate memory nodes. > > > I removed the "processor proximity domain valid" flag from the address > range structure of node2, and the GI is now its access0 initiator > instead of node2 itself. Looks like it confirms I was in case 2) > > Thanks > > Brice Cool. I was wondering if that change would work fine. It is a somewhat crazy setup so I didn't have an equivalent in my test set. Sounds like all is working as expected. Thanks, Jonathan
