On 10/29/19 12:43 PM, Dan Williams wrote: >> But some CPUs don't like to have two TLB entries for the same memory with >> different sizes at the same time. See for instance AMD erratum 383. > That basic description would seem to defeat most (all?) interesting > huge page use cases. For example dax makes no attempt to make sure > aliased mappings of pmem are the same size between the direct map that > the driver uses, and userspace dax mappings. So I assume there are > more details than "all aliased mappings must be the same size". These are about when large and small TLB entries could be held in the TLB at the same time for the same virtual address in the same process. It doesn't matter that two *different* mappings are using different page size. Imagine you were *just* changing the page size. Without these errata, you could just skip flushing the TLB. You might use the old hardware page size for a while, but it will be functionally OK. With these errata, we need to ensure in software that the old TLB entries for the old page size are flushed before the new page size is established.
