On Fri, 2019-10-04 at 09:22 +0200, Paolo Bonzini wrote: > On 03/10/19 23:23, Rick Edgecombe wrote: > > Since software would have previously received a #PF with the RSVD error code > > set, when the HW encountered any set bits in the region 51 to M, there was > > some > > internal discussion on whether this should have a virtual MSR for the OS to > > turn > > it on only if the OS knows it isn't relying on this behavior for bit M. The > > argument against needing an MSR is this blurb from the Intel SDM about > > reserved > > bits: > > "Bits reserved in the paging-structure entries are reserved for future > > functionality. Software developers should be aware that such bits may be > > used in > > the future and that a paging-structure entry that causes a page-fault > > exception > > on one processor might not do so in the future." > > > > So in the current patchset there is no MSR write required for the guest to > > turn > > on this feature. It will have this behavior whenever qemu is run with > > "-cpu +xo". > > I think the part of the manual that you quote is out of date. Whenever > Intel has "unreserved" bits in the page tables they have done that only > if specific bits in CR4 or EFER or VMCS execution controls are set; this > is a good thing, and I'd really like it to be codified in the SDM. > > The only bits for which this does not (and should not) apply are indeed > bits 51:MAXPHYADDR. But the SDM makes it clear that bits 51:MAXPHYADDR > are reserved, hence "unreserving" bits based on just a QEMU command line > option would be against the specification. So, please don't do this and > introduce an MSR that enables the feature. > > Paolo > Hi Paolo, Thanks for taking a look! Fair enough, MSR it is. Rick
