On Thu, Jan 10, 2019 at 03:40:04PM -0800, Dave Hansen wrote: > Anything else you do will have *some* reduced mitigation value, which > isn't a deal-breaker (to me at least). Some ideas: > > Take a look at the SWITCH_TO_KERNEL_CR3 in head_64.S. Every time that > gets called, we've (potentially) just done a user->kernel transition and > might benefit from flushing the TLB. We're always doing a CR3 write (on > Meltdown-vulnerable hardware) and it can do a full TLB flush based on if > X86_CR3_PCID_NOFLUSH_BIT is set. So, when you need a TLB flush, you > would set a bit that ADJUST_KERNEL_CR3 would see on the next > user->kernel transition on *each* CPU. Potentially, multiple TLB > flushes could be coalesced this way. The downside of this is that > you're exposed to the old TLB entries if a flush is needed while you are > already *in* the kernel. I would really prefer not to depend on the PTI crud for new stuff. We really want to get rid of that code on unaffected CPUs.
