On Thu, Dec 06, 2018 at 10:50:39PM +0000, Steve Capper wrote: > Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64 > entries (for the 48-bit case) to 1024 entries. This quantity, > PTRS_PER_PGD is used as follows to compute which PGD entry corresponds > to a given virtual address, addr: > > pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1) > > Userspace addresses are prefixed by 0's, so for a 48-bit userspace > address, uva, the following is true: > (uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1) > > In other words, a 48-bit userspace address will have the same pgd_index > when using PTRS_PER_PGD = 64 and 1024. > > Kernel addresses are prefixed by 1's so, given a 48-bit kernel address, > kva, we have the following inequality: > (kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1) > > In other words a 48-bit kernel virtual address will have a different > pgd_index when using PTRS_PER_PGD = 64 and 1024. > > If, however, we note that: > kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b) > and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE) > > We can consider: > (kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1) > = (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out > = 0x3C0 > > In other words, one can switch PTRS_PER_PGD to the 52-bit value globally > provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when > running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16). > > For kernel configuration where 52-bit userspace VAs are possible, this > patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the > 52-bit value. > > Suggested-by: Catalin Marinas <catalin.marinas@xxxxxxx> > Signed-off-by: Steve Capper <steve.capper@xxxxxxx> Reviewed-by: Catalin Marinas <catalin.marinas@xxxxxxx>
