On 12/6/18 2:39 PM, Jerome Glisse wrote:
> No if the 4 sockets are connect in a ring fashion ie:
> Socket0 - Socket1
> | |
> Socket3 - Socket2
>
> Then you have 4 links:
> link0: socket0 socket1
> link1: socket1 socket2
> link3: socket2 socket3
> link4: socket3 socket0
>
> I do not see how their can be an explosion of link directory, worse
> case is as many link directories as they are bus for a CPU/device/
> target.
This looks great. But, we don't _have_ this kind of information for any
system that I know about or any system available in the near future.
We basically have two different world views:
1. The system is described point-to-point. A connects to B @
100GB/s. B connects to C at 50GB/s. Thus, C->A should be
50GB/s.
* Less information to convey
* Potentially less precise if the properties are not perfectly
additive. If A->B=10ns and B->C=20ns, A->C might be >30ns.
* Costs must be calculated instead of being explicitly specified
2. The system is described endpoint-to-endpoint. A->B @ 100GB/s
B->C @ 50GB/s, A->C @ 50GB/s.
* A *lot* more information to convey O(N^2)?
* Potentially more precise.
* Costs are explicitly specified, not calculated
These patches are really tied to world view #1. But, the HMAT is really
tied to world view #1.
I know you're not a fan of the HMAT. But it is the firmware reality
that we are stuck with, until something better shows up. I just don't
see a way to convert it into what you have described here.
I'm starting to think that, no matter if the HMAT or some other approach
gets adopted, we shouldn't be exposing this level of gunk to userspace
at *all* since it requires adopting one of the world views.
