Re: [PATCH V4 4/6] arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD

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On Thu, Dec 06, 2018 at 11:50:12AM +0000, Catalin Marinas wrote:
> On Wed, Dec 05, 2018 at 04:41:43PM +0000, Steve Capper wrote:
> > diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
> > index 4128bec033f6..cd361dd16b12 100644
> > --- a/arch/arm64/include/asm/asm-uaccess.h
> > +++ b/arch/arm64/include/asm/asm-uaccess.h
> > @@ -14,11 +14,13 @@
> >  #ifdef CONFIG_ARM64_SW_TTBR0_PAN
> >  	.macro	__uaccess_ttbr0_disable, tmp1
> >  	mrs	\tmp1, ttbr1_el1			// swapper_pg_dir
> > +	restore_ttbr1 \tmp1
> >  	bic	\tmp1, \tmp1, #TTBR_ASID_MASK
> >  	sub	\tmp1, \tmp1, #RESERVED_TTBR0_SIZE	// reserved_ttbr0 just before swapper_pg_dir
> >  	msr	ttbr0_el1, \tmp1			// set reserved TTBR0_EL1
> >  	isb
> >  	add	\tmp1, \tmp1, #RESERVED_TTBR0_SIZE
> > +	offset_ttbr1 \tmp1
> >  	msr	ttbr1_el1, \tmp1		// set reserved ASID
> >  	isb
> >  	.endm
> > @@ -27,8 +29,10 @@
> >  	get_thread_info \tmp1
> >  	ldr	\tmp1, [\tmp1, #TSK_TI_TTBR0]	// load saved TTBR0_EL1
> >  	mrs	\tmp2, ttbr1_el1
> > +	restore_ttbr1 \tmp2
> >  	extr    \tmp2, \tmp2, \tmp1, #48
> >  	ror     \tmp2, \tmp2, #16
> > +	offset_ttbr1 \tmp2
> >  	msr	ttbr1_el1, \tmp2		// set the active ASID
> >  	isb
> >  	msr	ttbr0_el1, \tmp1		// set the non-PAN TTBR0_EL1
> 
> The patch looks alright but I think we can simplify it further if we add:
> 
> 	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
> 
> to the 52-bit Kconfig entry.

Ahh, thank you okay, I didn't make the connection that Privileged access
never was a mandatory feature in ARMv8.1.

Cheers,
-- 
Steve





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