On 10/25/18 at 10:24am, Kirill A. Shutemov wrote: > On Thu, Oct 25, 2018 at 10:18:09AM +0800, Baoquan He wrote: > > > We don't touch 4 pgd slot gap just before the direct mapping reserved > > > for a hypervisor, but move direct mapping by one slot instead. > > > > > > The LDT mapping is per-mm, so we cannot move it into P4D page table next > > > to CPU_ENTRY_AREA without complicating PGD table allocation for 5-level > > > paging. > > > > Here as discussed in private thread, at the first place you also agreed > > to put it in p4d entry next to CPU_ENTRY_AREA, but finally you changd > > mind, there must be some reasons when you implemented and investigated > > further to find out. Could you please say more about how it will > > complicating PGD table allocation for 5-level paging? Or give an use > > case where it will complicate? > > On 5-level machine all memory starting from CPU_ENTRY_AREA (and part of > KASAN memory) is in the same P4D page table. All this memory is shared > across all processes, we just copy PGD entry -- all proceses point to the > same P4D page table. (I leave out PTI from the picture for simplicity.) Yes, got it, I didn't notice this, thanks a lot.
