On Wed, Aug 22, 2018 at 10:11:41PM -0700, Linus Torvalds wrote: > On Wed, Aug 22, 2018 at 9:54 PM Benjamin Herrenschmidt <benh@xxxxxxxxxxx> wrote: > > > > > > So we do need a different flush instruction for the page tables vs. the > > normal TLB pages. > > Right. ARM wants it too. x86 is odd in that a regular "invlpg" already > invalidates all the internal tlb cache nodes. > > So the "new world order" is exactly that patch that PeterZ sent you, that adds a > > + unsigned int freed_tables : 1; > > to the 'struct mmu_gather', and then makes all those > pte/pmd/pud/p4d_free_tlb() functions set that bit. > > So I'm referring to the email PeterZ sent you in this thread that said: > > Nick, Will is already looking at using this to remove the synchronous > invalidation from __p*_free_tlb() for ARM, could you have a look to see > if PowerPC-radix could benefit from that too? > > Basically, using a patch like the below, would give your tlb_flush() > information on if tables were removed or not. > > then, in that model, you do *not* need to override these > pte/pmd/pud/p4d_free_tlb() macros at all (well, you *can* if you want > to, for doing games with the range modification, but let's sayt that > you don't need that right now). > > So instead, when you get to the actual "tlb_flush(tlb)", you do > exactly that - flush the tlb. And the mmu_gather structure shows you > how much you need to flush. If you see that "freed_tables" is set, > then you know that you need to also do the special instruction to > flush the inner level caches. The range continues to show the page > range. The only problem with this approach is that we've lost track of the granule size by the point we get to the tlb_flush(), so we can't adjust the stride of the TLB invalidations for huge mappings, which actually works nicely in the synchronous case (e.g. we perform a single invalidation for a 2MB mapping, rather than iterating over it at a 4k granule). One thing we could do is switch to synchronous mode if we detect a change in granule (i.e. treat it like a batch failure). Will
