On Wed, 22 Aug 2018 17:30:15 +0200 Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > Jann reported that x86 was missing required TLB invalidates when he > hit the !*batch slow path in tlb_remove_table(). > > This is indeed the case; RCU_TABLE_FREE does not provide TLB (cache) > invalidates, the PowerPC-hash where this code originated and the > Sparc-hash where this was subsequently used did not need that. ARM > which later used this put an explicit TLB invalidate in their > __p*_free_tlb() functions, and PowerPC-radix followed that example. So this is interesting, I _think_ a145abf12c did fix this bug for powerpc, but then it seem to have been re-broken by a46cc7a90f because that one defers the flush back to tlb_flush time. There was quite a lot of churn getting the radix MMU off the ground at that point though so I'm not 100% sure. But AFAIKS powerpc today has this same breakage, and this patch should fix it. I have a couple of patches that touch the same code I'll send, you might have some opinions on them. Thanks, Nick
