On Sun, Jan 21, 2018 at 6:20 PM, <hpa@xxxxxxxxx> wrote:
>
> No idea about Intel, but at least on Transmeta CPUs the limit check was asynchronous with the access.
Yes, but TMTA had a really odd uarch and didn't check segment limits natively.
When you do it in hardware. the limit check is actually fairly natural
to do early rather than late (since it acts on the linear address
_before_ base add and TLB lookup).
So it's not like it can't be done late, but there are reasons why a
traditional microarchitecture might always end up doing the limit
check early and so segmentation might be a good defense against
meltdown on 32-bit Intel.
Linus
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