On Tue, Dec 12, 2017 at 9:32 AM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > Peter and myself spent quite some time to figure out how to make CPUs cope > with a RO mapped LDT. > > While the initial trick of writing the ACCESS bit in a special fault > handler covers most cases, the tricky problem of CS/SS in return to user > space (IRET ...) was giving us quite some headache. > > Peter finally found a way to do so. Touching the CS/SS selectors with LAR > on the way out to user space makes it work w/o trouble. > > Contrary to the approach Andy was taking with storing the LDT in a special > map area, the following series uses a special mapping which is mapped > without the user bit and read only. This just ties the LDT to the process > which is the most natural way to do it, removes the requirement for special > pagetable code and works independent of pagetable isolation. > > This was tested on quite a range of Intel and AMD machines, but the test > coverage on 32bit is quite meager. I'll resurrect a few dust bricks > tomorrow. I think it's neat that you got this working. But it's like three times the size of my patch, is *way* more intrusive, and isn't obviously correct WRT IRET and load_gs_index(). So... how is it better than my patch? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
