On Thu, 2 Nov 2017, Andy Lutomirski wrote: > > On Nov 2, 2017, at 12:48 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > > > >> On Thu, 2 Nov 2017, Andy Lutomirski wrote: > >> I think we're far enough along here that it may be time to nail down > >> the memory layout for real. I propose the following: > >> > >> The user tables will contain the following: > >> > >> - The GDT array. > >> - The IDT. > >> - The vsyscall page. We can make this be _PAGE_USER. > > > > I rather remove it for the kaiser case. > > > >> - The TSS. > >> - The per-cpu entry stack. Let's make it one page with guard pages > >> on either side. This can replace rsp_scratch. > >> - cpu_current_top_of_stack. This could be in the same page as the TSS. > >> - The entry text. > >> - The percpu IST (aka "EXCEPTION") stacks. > > > > Do you really want to put the full exception stacks into that user mapping? > > I think we should not do that. There are two options: > > > > 1) Always use the per-cpu entry stack and switch to the proper IST after > > the CR3 fixup > > Can't -- it's microcode, not software, that does that switch. Well, yes. The micro code does the stack switch to ISTs but software tells it to do so. We write the IDT IIRC. > > 2) Have separate per-cpu entry stacks for the ISTs and switch to the real > > ones after the CR3 fixup. > > How is that simpler? Simpler is not the question. I want to avoid mapping the whole IST stacks. Thanks, tglx -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
