On Thu, Oct 12, 2017 at 06:07:36PM -0500, Eric W. Biederman wrote: > "Kirill A. Shutemov" <kirill@xxxxxxxxxxxxx> writes: > > > On Mon, Oct 09, 2017 at 09:54:53AM -0700, Dave Hansen wrote: > >> On 10/09/2017 09:09 AM, Kirill A. Shutemov wrote: > >> > Apart from trampoline itself we also need place to store top level page > >> > table in lower memory as we don't have a way to load 64-bit value into > >> > CR3 from 32-bit mode. We only really need 8-bytes there as we only use > >> > the very first entry of the page table. > >> > >> Oh, and this is why you have to move "lvl5_pgtable" out of the kernel image? > > > > Right. I initialize the new location of top level page table directly. > > So just a quick note. I have a fuzzy memory of people loading their > kernels above 4G physical because they did not have any memory below > 4G. > > That might be a very specialized case if my memory is correct because > cpu startup has to have a trampoline below 1MB. So I don't know how > that works. But I do seem to remember someone mentioning it. > > Is there really no way to switch to 5 level paging other than to drop to > 32bit mode and disable paging? The x86 architecture does some very > bizarre things so I can believe it but that seems like a lot of work to > get somewhere. The spec[1] is pretty clear on this, see section 2.2.2: The processor allows software to modify CR4.LA57 only outside of IA-32e mode. In IA-32e mode, an attempt to modify CR4.LA57 using the MOV CR instruction causes a general-protection exception (#GP). [1] https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf -- Kirill A. Shutemov -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
