On 07/06/2017 02:52 AM, Ram Pai wrote: > Add documentation updates that capture PowerPC specific changes. > > Signed-off-by: Ram Pai <linuxram@xxxxxxxxxx> > --- > Documentation/vm/protection-keys.txt | 85 ++++++++++++++++++++++++++-------- > 1 files changed, 65 insertions(+), 20 deletions(-) > > diff --git a/Documentation/vm/protection-keys.txt b/Documentation/vm/protection-keys.txt > index b643045..d50b6ab 100644 > --- a/Documentation/vm/protection-keys.txt > +++ b/Documentation/vm/protection-keys.txt > @@ -1,21 +1,46 @@ > -Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature > -which will be found on future Intel CPUs. > +Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature found in > +new generation of intel CPUs and on PowerPC 7 and higher CPUs. > > Memory Protection Keys provides a mechanism for enforcing page-based > -protections, but without requiring modification of the page tables > -when an application changes protection domains. It works by > -dedicating 4 previously ignored bits in each page table entry to a > -"protection key", giving 16 possible keys. > - > -There is also a new user-accessible register (PKRU) with two separate > -bits (Access Disable and Write Disable) for each key. Being a CPU > -register, PKRU is inherently thread-local, potentially giving each > -thread a different set of protections from every other thread. > - > -There are two new instructions (RDPKRU/WRPKRU) for reading and writing > -to the new register. The feature is only available in 64-bit mode, > -even though there is theoretically space in the PAE PTEs. These > -permissions are enforced on data access only and have no effect on > +protections, but without requiring modification of the page tables when an > +application changes protection domains. > + > + > +On Intel: > + > + It works by dedicating 4 previously ignored bits in each page table > + entry to a "protection key", giving 16 possible keys. > + > + There is also a new user-accessible register (PKRU) with two separate > + bits (Access Disable and Write Disable) for each key. Being a CPU > + register, PKRU is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. > + > + There are two new instructions (RDPKRU/WRPKRU) for reading and writing > + to the new register. The feature is only available in 64-bit mode, > + even though there is theoretically space in the PAE PTEs. These > + permissions are enforced on data access only and have no effect on > + instruction fetches. > + > + > +On PowerPC: > + > + It works by dedicating 5 page table entry bits to a "protection key", > + giving 32 possible keys. > + > + There is a user-accessible register (AMR) with two separate bits; > + Access Disable and Write Disable, for each key. Being a CPU > + register, AMR is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. NOTE: > + Disabling read permission does not disable write and vice-versa. We can only enable/disable entire access or write. Then how read permission can be changed with protection keys directly ? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
