On Wed, Jun 21, 2017 at 10:43 AM, Borislav Petkov <bp@xxxxxxxxx> wrote:
> On Tue, Jun 20, 2017 at 10:22:10PM -0700, Andy Lutomirski wrote:
>> - * The x86 doesn't have a mmu context, but
>> - * we put the segment information here.
>> + * x86 has arch-specific MMU state beyond what lives in mm_struct.
>> */
>> typedef struct {
>> + /*
>> + * ctx_id uniquely identifies this mm_struct. A ctx_id will never
>> + * be reused, and zero is not a valid ctx_id.
>> + */
>> + u64 ctx_id;
>> +
>> + /*
>> + * Any code that needs to do any sort of TLB flushing for this
>> + * mm will first make its changes to the page tables, then
>> + * increment tlb_gen, then flush. This lets the low-level
>> + * flushing code keep track of what needs flushing.
>> + *
>> + * This is not used on Xen PV.
>> + */
>> + atomic64_t tlb_gen;
>
> Btw, can this just be a 4-byte int instead? I.e., simply atomic_t. I
> mean, it should be enough for all the TLB generations in flight, no?
There can only be NR_CPUS generations that actually mean anything at
any given time, but I think they can be arbitrarily discontinuous.
Imagine a malicious program that does:
set affiinitiy to CPU 1
mmap()
set affinity to CPU 0
for (i = 0; i < (1ULL<<32); i++) {
munmap();
mmap();
}
set affinity to CPU 1
With just atomic_t, this could blow up.
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