On Wed, May 10, 2017 at 02:00:26PM -0400, David Miller wrote: > From: Matthew Wilcox <willy@xxxxxxxxxxxxx> > Date: Wed, 10 May 2017 10:17:03 -0700 > > On Wed, May 10, 2017 at 11:19:43AM -0400, David Miller wrote: > >> I guess it might be clearer if you understand what the block > >> initializing stores do on sparc64. There are no memory accesses at > >> all. > >> > >> The cpu just zeros out the cache line, that's it. > >> > >> No L3 cache line is allocated. So this "wipe everything" behavior > >> will not happen in the L3. > > > > There's either something wrong with your explanation or my reading > > skills :-) > > > > "There are no memory accesses" > > "No L3 cache line is allocated" > > > > You can have one or the other ... either the CPU sends a cacheline-sized > > write of zeroes to memory without allocating an L3 cache line (maybe > > using the store buffer?), or the CPU allocates an L3 cache line and sets > > its contents to zeroes, probably putting it in the last way of the set > > so it's the first thing to be evicted if not touched. > > There is no conflict in what I said. > > Only an L2 cache line is allocated and cleared. L3 is left alone. I thought SPARC had inclusive caches. So allocating an L2 cacheline would necessitate allocating an L3 cacheline. Or is this an exception to the normal order of things? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
