On Tue, Feb 7, 2017 at 10:56 AM, Andy Lutomirski <luto@xxxxxxxxxx> wrote: > Quite a few people have expressed interest in enabling PCID on (x86) > Linux. Here's the code: > > https://git.kernel.org/cgit/linux/kernel/git/luto/linux.git/log/?h=x86/pcid > > The main hold-up is that the code needs to be reviewed very carefully. > It's quite subtle. In particular, "x86/mm: Try to preserve old TLB > entries using PCID" ought to be looked at carefully to make sure the > locking is right, but there are plenty of other ways this this could > all break. > > Anyone want to take a look or maybe scare up some other reviewers? > (Kees, you seemed *really* excited about getting this in.) Nadav pointed out that this doesn't work right with ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH. Mel, here's the issue: I want to add ASID (Intel calls it PCID) support to x86. This means that "flush the TLB on a given CPU" will no longer be a particularly well defined operation because it's not clear which ASID tag to flush. Instead there's "flush the TLB for a given mm on a given CPU". If I'm understanding the batched flush code, all it's trying to do is to flush more than one mm at a time. Would it make sense to add a new arch API to flush more than one mm? Presumably it would take a linked list, and the batched flush code would fall back to flushing in pieces if it can't allocate a new linked list node when needed. Thoughts? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>
