* Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx> wrote:
> Larger address spaces mean larger MPX bounds table sizes. This
> tracks which size tables we are using.
>
> "MAWA" is what the hardware documentation calls this feature:
> MPX Address-Width Adjust. We will carry that nomenclature throughout
> this series.
>
> The new field will be optimized and get packed into 'bd_addr' in a later
> patch. But, leave it separate for now to make the series simpler.
>
> ---
>
> b/arch/x86/include/asm/mmu.h | 1 +
> b/arch/x86/include/asm/mpx.h | 9 +++++++++
> 2 files changed, 10 insertions(+)
>
> diff -puN arch/x86/include/asm/mmu.h~mawa-020-mmu_context-mawa arch/x86/include/asm/mmu.h
> --- a/arch/x86/include/asm/mmu.h~mawa-020-mmu_context-mawa 2017-01-26 14:31:32.643673297 -0800
> +++ b/arch/x86/include/asm/mmu.h 2017-01-26 14:31:32.647673476 -0800
> @@ -34,6 +34,7 @@ typedef struct {
> #ifdef CONFIG_X86_INTEL_MPX
> /* address of the bounds directory */
> void __user *bd_addr;
> + int mpx_mawa;
-ENOCOMMENT.
Plus 'int' looks probably wrong, unless the hardware really wants signed shift
values. (whatever 'mpx_mawa' is.)
Plus, while Intel is free to use sucky acronyms such as MAWA, could we please name
this and related functionality sensibly: mpx_table_size or mpx_table_shift or
such? The data structure comment can point out that Intel calls this 'MAWA'.
(Also, the changelog refers to a later change, which never happens in this
series.)
Thanks,
Ingo
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