On Thu, Jun 30, 2016 at 5:12 PM, Dave Hansen <dave@xxxxxxxx> wrote: > > From: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx> > > The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights > Landing) has an erratum where a processor thread setting the Accessed > or Dirty bits may not do so atomically against its checks for the > Present bit. This may cause a thread (which is about to page fault) > to set A and/or D, even though the Present bit had already been > atomically cleared. So I don't think your approach is wrong, but I suspect this is overkill, and what we should instead just do is to not use the A/D bits at all in the swap representation. The swap-entry representation was a bit tight on 32-bit page table entries, but in 64-bit ones, I think we have tons of bits, don't we? So we could decide just to not use those two bits on x86. It's not like anybody will ever care about 32-bit page tables on Knights Landing anyway. So rather than add this kind of complexity and worry, how about just simplifying the problem? Or was there some discussion or implication I missed? Linus -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx"> email@xxxxxxxxx </a>