Re: x86: possible store-tearing in native_set_pte?

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Resending with fixed formatting (sorry for that):

Can someone please explain why it is ok for native_set_pte to assign
the PTE without WRITE_ONCE() ?

Isn't it possible for a PTE write to be torn, and the PTE to be
prefetched in between (or even used for translation by another core)?

I did not encounter this case, but it seems to me possible according
to the documentation:

Intel SDM 4.10.2.3 "Detail of TLB Use": "The processor may cache
translations required for prefetches and for accesses ... that would
never actually occur in the executed code path."

Documentation/memory-barriers.txt: "The compiler is within its rights
to invent stores to a variable".

Thanks,
Nadav

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