On Fri, Mar 21, 2025 at 01:46:27PM +0000, Caleb James DeLisle wrote: > Document the device tree binding for the interrupt controller in the > EcoNet EN751221 MIPS SoC. > > Signed-off-by: Caleb James DeLisle <cjd@xxxxxxxx> > --- > If anyone is aware of a standard name for this "shadow interrupt" pattern, > please let me know and I will re-send with updated naming. > --- > .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > new file mode 100644 > index 000000000000..1b0f262c9630 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: EcoNet EN751221 Interrupt Controller > + > +maintainers: > + - Caleb James DeLisle <cjd@xxxxxxxx> > + > +description: | Don't need '|' if no formatting. > + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller > + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can > + be routed to either VPE but not both, so to support per-CPU interrupts, a > + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For > + lack of a better term we call these "shadow interrupts". The assignment of > + shadow interrupts is defined by the SoC integrator when wiring the interrupt > + lines, so they are configurable in the device tree. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + const: econet,en751221-intc > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 1 > + > + interrupt-controller: true > + > + interrupts: > + maxItems: 1 > + description: Interrupt line connecting this controller to its parent. > + > + econet,shadow-interrupts: > + $ref: /schemas/types.yaml#/definitions/uint32-array Looks like uint32-matrix to me as it pairs of u32's. > + description: | > + An array of interrupt number pairs where each pair represents a shadow > + interrupt relationship. The first number in each pair is the primary IRQ, > + and the second is its shadow IRQ used for VPE#1 control. For example, > + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but > + when VPE#1 requests IRQ 8, it will use manipulate the IRQ 3 mask bit. > + maxItems: 40 > + items: > + minimum: 0 > + maximum: 40 Then this would be: minItems: 1 maxItems: 40 items: items: - description: primary IRQ - description: shadow IRQ (Feel free to expand the descriptions) > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - "#interrupt-cells" > + - interrupt-parent Generally, interrupt-parent is never required. It can be in a parent node for example. > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + intc: interrupt-controller@1fb40000 { Drop unused labels (intc). > + compatible = "econet,en751221-intc"; > + reg = <0x1fb40000 0x100>; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; > + > + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; > + }; > +... > -- > 2.30.2 >
