Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC. Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx> --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index a84e6e720619ef99e1405ae6296d8bad1aa3fa23..420cb27607bfdd8d5ea510fb668b0a1c85dd7d83 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -77,6 +77,8 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; + ethernet0 = &macb0; + ethernet1 = &macb1; }; cpu_intc: interrupt-controller { @@ -178,6 +180,38 @@ timer { clocks = <&olb EQ5C_CPU_CORE0>; }; }; + + macb0: ethernet@2a00000 { + compatible = "mobileye,eyeq5-gem"; + reg = <0x0 0x02a00000 0x0 0x4000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, /* queue0 */ + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, /* queue1 */ + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, /* queue2 */ + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; /* queue3 */ + clock-names = "pclk", "hclk", "tsu_clk"; + clocks = <&pclk>, <&pclk>, <&tsu_clk>; + dma-coherent; + nvmem-cells = <ð0_mac>; + nvmem-cell-names = "mac-address"; + mobileye,olb = <&olb 0x128 0x134>; + }; + + macb1: ethernet@2b00000 { + compatible = "mobileye,eyeq5-gem"; + reg = <0x0 0x02b00000 0x0 0x4000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, /* queue0 */ + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, /* queue1 */ + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, /* queue2 */ + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; /* queue3 */ + clock-names = "pclk", "hclk", "tsu_clk"; + clocks = <&pclk>, <&pclk>, <&tsu_clk>; + dma-coherent; + nvmem-cells = <ð1_mac>; + nvmem-cell-names = "mac-address"; + mobileye,olb = <&olb 0x12c 0x138>; + }; }; }; -- 2.48.1