Add device tree binding documentation for the high-precision timer (HPT) in the EcoNet EN751221 SoC. Signed-off-by: Caleb James DeLisle <cjd@xxxxxxxx> --- .../bindings/timer/econet,timer-hpt.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml diff --git a/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml new file mode 100644 index 000000000000..8b7ff9bce947 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/econet,timer-hpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet High Precision Timer (HPT) + +maintainers: + - Calev James DeLisle <cjd@xxxxxxxx> + +description: | + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE + count/compare registers and a per-CPU control register, with a single interrupt + line using a percpu-devid interrupt mechanism. + +properties: + compatible: + const: econet,timer-hpt + + reg: + minItems: 1 + maxItems: 2 + description: | + Physical base address and size of the timer's register space. On 34Kc + processors, a single region is used. On 1004Kc processors, two regions are + used, one for each core. + + interrupts: + maxItems: 1 + description: | + The interrupt number for the timer. This is a percpu-devid interrupt shared + across CPUs. + + clocks: + maxItems: 1 + description: | + A clock to get the frequency of the timer. + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer_hpt@1fbf0400 { + compatible = "econet,timer-hpt"; + reg = <0x1fbf0400 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +... -- 2.30.2
