On Wed, 15 Jan 2025, Arnd Bergmann wrote:
> On Malta, I see a very strange
>
> isa {
> compatible = "isa";
> ranges = <1 0 0 0x1000>;
> };
>
> which maps the first 4096 port numbers into cpu_addr=0x0. The
> actual port window appears to be at a board specific location
>
> #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
> #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
> #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
The system controller (PCI host bridge) is on the CPU core card along
with the CPU and DRAM, so you get what you plug into the Malta baseboard,
which is where the rest of the system resides connected via PCI and CBUS
(which is a platform I/O bus wiring boot Flash, an auxiliary debug UART,
also usable by Linux, and a bunch of simple peripherals needed for board
setup and diagnostic output before PCI can be accessed, all on the Malta
baseboard).
> So e.g. on Bonito, the ranges property would have to be
>
> ranges = <1 0 0x1fd00000 0x1000>;
>
> Not sure if this is patched in by the bootloader, or where the
> corresponding window for PCI gets defined, but I suspect that
> the reason for the regression is that the caller of
> pci_address_to_pio() accidentally passed in '0' instead of
> the physical address, and it happened to work because of the
> missing PCI_IOBASE definition but broke after that got defined.
The windows are retrieved from hardware; cf. arch/mips/pci/pci-malta.c.
Maciej
