hi thanks for your clarifications. I bought this book UNIX Systems for Modern Architectures (1994), by Curt Schimmel (found a few on Amazon and eBay com, ex library books) Yesterday I also printed a copy of the MIPS R10K user manual. There are a lot of things I don't know, to learn of course the fact that not all R10K CPUs work the same, as Kumba pointed out, is an additional complication in systems like IP28 that are not cache-coherent On Wed, Oct 30, 2024 at 12:59 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote: > > > > 在2024年10月29日十月 下午8:56，Jiaxun Yang写道： > [...] > >> Worse still, if the speculative approach involved a Conditional Store > >> (SC): will it be restored? No, because - the manual says - if the > >> cache is involved, then it won't be restored, so this is a real mess > >> that needs at least a sw barrier. > > > > I don't really know R10k implementation details, but IMHO since SC can > > only change a cacheline between two exclusive states, it doesn't matter > > that much.... > > For LLSC I'm wrong. > > See: https://inbox.sourceware.org/gcc-patches/490A90F4.6040601@xxxxxxxxxx/ > > Thanks > > -- > - Jiaxun
