From: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status
for Hardware Cache Initialization (HCI). This commit adds a property
to acknowledge this issue, which enables the use of the second CPU
cluster.
Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
Signed-off-by: Aleksandar Rikalo <arikalo@xxxxxxxxx>
Tested-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
---
arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 1db3c3cda2e3..4ea85dfd4eed 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -18,6 +18,7 @@ cpu@0 {
compatible = "img,i6500";
reg = <0>;
clocks = <&occ_cpu>;
+ cm3-l2-config-hci-broken;
};
};
--
2.25.1
