On Thu, 05 Sep 2024 14:33:07 +0100 Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote: > Enable rust for linux by implement generate_rust_target.rs > and select relevant Kconfig options. > > We don't use builtin target as there is no sutiable baremetal > target for us that can cover all ISA variants supported by kernel. > > Link: https://github.com/Rust-for-Linux/linux/issues/107 > Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> > --- > v2: > - Add micromips flags > - Sync issues with upstream > --- > Documentation/rust/arch-support.rst | 1 + > .../translations/zh_CN/rust/arch-support.rst | 1 + > arch/mips/Kconfig | 2 + > scripts/generate_rust_target.rs | 68 ++++++++++++++++++++++ > 4 files changed, 72 insertions(+) > > diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst > index 750ff371570a..ab6c0ae5a407 100644 > --- a/Documentation/rust/arch-support.rst > +++ b/Documentation/rust/arch-support.rst > @@ -17,6 +17,7 @@ Architecture Level of support Constraints > ============= ================ ============================================== > ``arm64`` Maintained Little Endian only. > ``loongarch`` Maintained \- > +``mips`` Maintained \- > ``riscv`` Maintained ``riscv64`` only. > ``um`` Maintained \- > ``x86`` Maintained ``x86_64`` only. > diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst > index abd708d48f82..1eaa6c3297ac 100644 > --- a/Documentation/translations/zh_CN/rust/arch-support.rst > +++ b/Documentation/translations/zh_CN/rust/arch-support.rst > @@ -21,6 +21,7 @@ > ============= ================ ============================================== > ``arm64`` Maintained 只有小端序 > ``loongarch`` Maintained \- > +``mips`` Maintained \- > ``riscv`` Maintained 只有 ``riscv64`` > ``um`` Maintained 只有 ``x86_64`` > ``x86`` Maintained 只有 ``x86_64`` > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 43da6d596e2b..a91f0a4fd8e9 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -90,6 +90,8 @@ config MIPS > select HAVE_PERF_USER_STACK_DUMP > select HAVE_REGS_AND_STACK_ACCESS_API > select HAVE_RSEQ > + select HAVE_RUST > + select HAVE_GENERATE_RUST_TARGET > select HAVE_SPARSE_SYSCALL_NR > select HAVE_STACKPROTECTOR > select HAVE_SYSCALL_TRACEPOINTS > diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs > index 863720777313..bbdf8a4dd169 100644 > --- a/scripts/generate_rust_target.rs > +++ b/scripts/generate_rust_target.rs > @@ -141,6 +141,13 @@ fn has(&self, option: &str) -> bool { > let option = "CONFIG_".to_owned() + option; > self.0.contains_key(&option) > } > + > + /// Returns the value of the option in the configuration. > + /// The argument must be passed without the `CONFIG_` prefix. > + fn get(&self, option: &str) -> Option<&String> { > + let option = "CONFIG_".to_owned() + option; > + self.0.get(&option) I know you follow the code style above, but this should be let option = format!("CONFIG_{option}"); > + } > } > > fn main() { > @@ -203,6 +210,67 @@ fn main() { > ts.push("target-pointer-width", "32"); > } else if cfg.has("LOONGARCH") { > panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target"); > + } else if cfg.has("MIPS") { > + let mut features = "+soft-float,+noabicalls".to_string(); > + > + if cfg.has("CPU_MICROMIPS") { > + features += ",+micromips"; > + } > + > + if cfg.has("64BIT") { > + ts.push("arch", "mips64"); > + ts.push("abi", "abi64"); > + cfg.get("TARGET_ISA_REV").map(|isa_rev| { if let Some(isa_rev) = cfg.get("TARGET_ISA_REV") { ... } > + let feature = match isa_rev.as_str() { > + "1" => ",+mips64", > + "2" => ",+mips64r2", > + "5" => ",+mips64r5", > + "6" => ",+mips64r6", > + _ => ",+mips3", > + }; > + features += feature; > + }); > + > + ts.push("features", features); > + if cfg.has("CPU_BIG_ENDIAN") { > + ts.push( > + "data-layout", > + "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", > + ); > + ts.push("llvm-target", "mips64-unknown-linux-gnuabi64"); > + } else { > + ts.push( > + "data-layout", > + "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", > + ); > + ts.push("llvm-target", "mips64el-unknown-linux-gnuabi64"); > + } > + ts.push("target-pointer-width", "64"); > + } else { > + ts.push("arch", "mips"); > + cfg.get("TARGET_ISA_REV").map(|isa_rev| { ditto > + let feature = match isa_rev.as_str() { > + "1" => ",+mips32", > + "2" => ",+mips32r2", > + "5" => ",+mips32r5", > + "6" => ",+mips32r6", > + _ => ",+mips2", > + }; > + features += feature; > + }); > + > + ts.push("features", features); > + if cfg.has("CPU_BIG_ENDIAN") { > + ts.push("data-layout", > + "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); > + ts.push("llvm-target", "mips-unknown-linux-gnu"); > + } else { > + ts.push("data-layout", > + "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); > + ts.push("llvm-target", "mipsel-unknown-linux-gnu"); > + } > + ts.push("target-pointer-width", "32"); > + } > } else { > panic!("Unsupported architecture"); > } > Best, Gary
