On Thu, Jun 13, 2024 at 08:40:18PM +0100, Jiaxun Yang wrote: > > > 在2024年6月13日六月 下午7:59，Rob Herring写道： > > On Wed, Jun 12, 2024 at 05:59:24PM +0100, Jiaxun Yang wrote: > >> > >> > >> 在2024年6月12日六月 下午5:39，Conor Dooley写道： > >> > On Wed, Jun 12, 2024 at 12:56:26PM +0100, Jiaxun Yang wrote: > >> >> This compatible is used by boston.dts. > >> >> > >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> > >> >> --- > >> >> note: This is a wildcard compatible for all MIPS CPUs, > >> >> I think we should use something like "riscv" for riscv. > >> > > >> > riscv systems, other than simulators etc are not meant to use the > >> > "riscv" compatible. All of the real CPUs use "vendor,cpu", "riscv". > >> > I'd suggest you add specific compatibles for your CPUs. > >> > >> Boston can be combined with many different CPUs, thus we need to have > >> such compatibles. > > > > Then you'll need different DTs. Different h/w, different DT. > > The board have 9 CPU types in total, with hundreds of different possible > CPU topologies. Maintaining separate DT for them seems impossible in kernel. But you could definitely add 9 different compatibles for each of these different CPUs. > We can potentially patch this in bootloader, but for existing firmware it's > being doing like this for years. I can see for RISC-V QEMU generated DTB is > using a single "riscv" compatible and I do think it's a similar problem. That "riscv" compatible is only supposed to be used for simulators/software models. Real CPUs are not meant to use it. AFAICT, your boston is a real platform, even if the CPUs are implemented on an FPGA they should still have one. If you take the OpenC906 RISC-V CPU and put it on an FPGA, you're still meant to put "thead,c906" in your DT. > I think it's better to document it and warn people only to use it in limited > circumstances, instead of keeping such usage in grey area. > > > > > No way we're taking a generic compatible like this.
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