On Sat, 11 May 2024, Jiaxun Yang wrote: > Increase frequency addend dividend to 100000000 (10MHz) to The value of 100000000 is AFAICT 100MHz. > diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c > index edc4afc080fa..262896871351 100644 > --- a/arch/mips/kernel/csrc-r4k.c > +++ b/arch/mips/kernel/csrc-r4k.c > @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) > return -ENXIO; > > /* Calculate a somewhat reasonable rating value */ > - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; > + clocksource_mips.rating = 200; > + clocksource_mips.rating += clamp(mips_hpt_frequency / 100000000, 0, 99); And FAOD the code change does match it. Maciej