On 5/9/24 13:47, Christian Marangi wrote:
Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
Acked-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx> -- Florian
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