On Tue, Apr 30, 2024 at 06:45:58PM +0300, Siarhei Volkau wrote: > MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load > and right after move to HI/LO will usually stall the pipeline for > significant amount of time. Let's take it into account and separate > loads and mthi/lo in instruction sequence. > > The patch uses t6 and t7 registers as temporaries in addition to t8. > > The patch tries to deal with SmartMIPS, but I know little about and > haven't tested it. > > Changes in v2: > - clear separation of actions for SmartMIPS and pre-MIPSR6. > > Signed-off-by: Siarhei Volkau <lis8215@xxxxxxxxx> > --- > arch/mips/include/asm/stackframe.h | 19 +++++++++++-------- > 1 file changed, 11 insertions(+), 8 deletions(-) > applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
