On Wed, Jan 10, 2024 at 10:38:57AM +0200, Tony Lindgren wrote: > * Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> [240109 19:53]: > > On 09/01/2024 18:19, Andrew Davis wrote: > > > The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from > > > multiple vendors. Describe how the SGX GPU is integrated in these SoC, > > > including register space and interrupts. Clocks, reset, and power domain > > > information is SoC specific. > > > > > > Signed-off-by: Andrew Davis <afd@xxxxxx> > > > Reviewed-by: Javier Martinez Canillas <javierm@xxxxxxxxxx> > > > > > > > + clock-names: > > > + minItems: 1 > > > + items: > > > + - const: core > > > + - const: mem > > > + - const: sys > > > > There are no devices currently using third clock, but I assume it is > > expected or possible. > > I think the third clock is typically merged with one of the two clocks but > yeah possibly it's a separate clocke in some cases. > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > Looks good to me too. > > So for merging these, as many of the changes touch the omap variants, I > could set up an immutable branch with all the changes after -rc1. Or I can > ack the patches too if somebody has better ideas. Just take all but patches 10 and 11. I don't think it matters if the binding is there for them as long as it is all there in next. No one is paying that close attention to the warnings I think. Rob
