Hello Jiaxun, > 在2023年10月9日十月 下午4:59，Gregory CLEMENT写道： >> Hello Jiaxun, >> >>> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道： >>>> From: Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxx> >>>> >>>> Support platforms where RAM is mapped beyond 32-bit. >>>> >>>> The kernel parameter ddr32_alias allows to setup the alias to point >>>> outside the first 4 GB of memory. >>> >>> Are you trying to fix the problem that if kernel text is loaded in >>> XKPHYS there is no way to to set EBASE to that region? >> >> Yes that exactly we try to fix. >> >>> >>> The common practice for other 64bit MIPS system is to load kernel >>> in KSEG0 and add low 4G mirror with rest of the high memory to buddy >>> system. By doing this Kernel still have access to all memory beyond >>> 32 bit, the only draw back is Kernel's text and data can't be relocted >>> beyond 32-bit. >>> >>> Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit >>> on performance, so I think you shouldn't try to load kernel into XKPHYS >>> without a good reason, but it might be helpful to add a BUG_ON at >>> CPS driver to handle such situation. >> >> I guess that being in KSEG0 allows to use shorter pointer. But in our >> case the RAM is physically connected beyond 32bits, so it is not >> accessible in KSEG0. > > For most system there should be a mirror of part of DDR which is accessible > at KSEG0 and kernel runs from here. As per my interpretion of your code EyeQ5 > is also doing this? If not could you please briefly describe the memory map? > > For Kernel in KSEG0 the pointer is still 64bit but we can use fewer inst > to load ABS pointer into register, see [1]. > There is a kind of mirror but its physical address start at 0x8000000 so beyond the first 512MBytes that are used for KSEG0. In short the 32bits mapping is the following: - the controllers registers of the SoC are located until 0x8000000, - then from 0x8000000 to 0x10000000 there is the alias to low addresses of the DDR - then the SPIflash is mapped to from 0x10000000 to 0x20000000 - after the PCIe Memory 32-bit addr space is from 0x20000000 to 0x40000000 Gregory > [1]: https://elinux.org/images/1/1f/New-tricks-mips-linux.pdf -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
